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1. 发明申请

US20050099836A1 Isolation device over field in a memory device 失效
标题翻译：隔离设备在存储设备中的字段
公开(公告)号：US20050099836A1
公开(公告)日：2005-05-12
申请号：US10998483
申请日：2004-11-29
申请人： Luan Tran , Stephen Porter , Scot Graham , Steven Howell
发明人： Luan Tran , Stephen Porter , Scot Graham , Steven Howell
IPC分类号： G11C7/12 , G11C7/18 , G11C11/4097 , G11C11/24 , G11C5/06
CPC分类号： G11C7/02 , G11C7/12 , G11C7/18 , G11C11/401 , G11C11/4097 , G11C29/816 , G11C2207/002 , G11C2207/005 , Y10S257/906
摘要： A memory device includes isolation devices located between memory cells. A plurality of isolation lines connects the isolation devices to a positive voltage during normal operations but still keeps the isolation devices in the off state to provide isolation between the memory cells. A current control circuit is placed between the isolation lines and a power node for reducing a current flowing between the isolation lines and the power node in case a deflect occurs at any one of isolation devices.
摘要翻译：存储器件包括位于存储器单元之间的隔离器件。多个隔离线在正常操作期间将隔离装置连接到正电压，但是仍然使隔离装置保持在关闭状态以提供存储单元之间的隔离。在隔离线路和电源节点之间放置电流控制电路，用于在任何一个隔离装置发生偏转的情况下减少在隔离线路与功率节点之间流动的电流。

2. 发明申请

US20060139988A1 Isolation device over field in a memory device 有权
标题翻译：隔离设备在存储设备中的字段
公开(公告)号：US20060139988A1
公开(公告)日：2006-06-29
申请号：US11358234
申请日：2006-02-21
申请人： Luan Tran , Stephen Porter , Scot Graham , Steven Howell
发明人： Luan Tran , Stephen Porter , Scot Graham , Steven Howell
IPC分类号： G11C11/24 , G11C11/401
CPC分类号： G11C7/02 , G11C7/12 , G11C7/18 , G11C11/401 , G11C11/4097 , G11C29/816 , G11C2207/002 , G11C2207/005 , Y10S257/906
摘要： A memory device includes isolation devices located between-memory cells. A plurality of isolation lines connects the isolation devices to a positive voltage during normal operations but still keeps the isolation devices in the off state to provide isolation between the memory cells. A current control circuit is placed between the isolation lines and a power node for reducing a current flowing between the isolation lines and the power node in case a deflect occurs at any one of isolation devices.
摘要翻译：存储器件包括位于存储器单元之间的隔离器件。多个隔离线在正常操作期间将隔离装置连接到正电压，但是仍然使隔离装置保持在关闭状态以提供存储单元之间的隔离。在隔离线路和电源节点之间放置电流控制电路，用于在任何一个隔离装置发生偏转的情况下减少在隔离线路与功率节点之间流动的电流。

3. 发明授权

US08216949B2 Method for integrated circuit fabrication using pitch multiplication 有权
标题翻译：使用音调倍数的集成电路制作方法
公开(公告)号：US08216949B2
公开(公告)日：2012-07-10
申请号：US12707560
申请日：2010-02-17
申请人： Mirzafer K Abatchev , Gurtej Sandhu , Luan Tran , William T Rericha , D. Mark Durcan
发明人： Mirzafer K Abatchev , Gurtej Sandhu , Luan Tran , William T Rericha , D. Mark Durcan
IPC分类号： H01L21/302 , H01L21/461
CPC分类号： H01L21/0337 , H01L21/0332 , H01L21/0338 , H01L21/3081 , H01L21/3086 , H01L21/3088 , H01L21/31144 , H01L21/32139 , Y10S438/947 , Y10S438/95
摘要： A method lor integrated circuit fabrication is disclosed. A spacer pattern is provided including a plurality ot spacers in an array region of a partially-fabricated integrated circuit. Each spacer is at least partly defined by opposing open volumes extending along lengths of the spacers. A pattern is subsequently defined in a periphery region of the partially-fabricated integrated circuit. A consolidated pattern is formed by concurrently transferring the spacer pattern and the pattern in the periphery region into an underlying masking layer. The consolidated pattern is transferred to an underlying substrate.
摘要翻译：公开了一种用于集成电路制造的方法。提供了一种间隔图案，其包括在部分制造的集成电路的阵列区域中的多个间隔物。每个间隔物至少部分地通过沿间隔物的长度延伸的相对的开放体积限定。随后在部分制造的集成电路的外围区域中限定图案。通过将间隔物图案和外围区域中的图案同时转移到下面的掩模层中形成固结图案。固结图案转移到下面的基底。

4. 发明授权

US08119535B2 Pitch reduced patterns relative to photolithography features 有权
标题翻译：相对于光刻特征的间距减小
公开(公告)号：US08119535B2
公开(公告)日：2012-02-21
申请号：US12636581
申请日：2009-12-11
申请人： Luan Tran , William T Rericha , John Lee , Ramakanth Alapati , Sheron Honarkhah , Shuang Meng , Puneet Sharma , Jingyi Bai , Zhiping Yin , Paul Morgan , Mirzafer K Abatchev , Gurtej S Sandhu , D. Mark Durcan
发明人： Luan Tran , William T Rericha , John Lee , Ramakanth Alapati , Sheron Honarkhah , Shuang Meng , Puneet Sharma , Jingyi Bai , Zhiping Yin , Paul Morgan , Mirzafer K Abatchev , Gurtej S Sandhu , D. Mark Durcan
IPC分类号： H01L21/302 , H01L21/461
CPC分类号： H01L21/0338 , H01L21/0337 , H01L21/3086 , H01L21/3088
摘要： Differently-sized features of an integrated circuit are formed by etching a substrate using a mask which is formed by combining two separately formed patterns. Pitch multiplication is used to form the relatively small features of the first pattern and conventional photolithography used to form the relatively large features of the second pattern. Pitch multiplication is accomplished by patterning a photoresist and then etching that pattern into an amorphous carbon layer. Sidewall spacers are then formed on the sidewalls of the amorphous carbon. The amorphous carbon is removed, leaving behind the sidewall spacers, which define the first mask pattern. A bottom anti-reflective coating (BARC) is then deposited around the spacers to form a planar surface and a photoresist layer is formed over the BARC. The photoresist is next patterned by conventional photolithography to form the second pattern, which is then is transferred to the BARC. The combined pattern made out by the first pattern and the second pattern is transferred to an underlying amorphous silicon layer and the pattern is subjected to a carbon strip to remove BARC and photoresist material. The combined pattern is then transferred to the silicon oxide layer and then to an amorphous carbon mask layer. The combined mask pattern, having features of difference sizes, is then etched into the underlying substrate through the amorphous carbon hard mask layer.
摘要翻译：通过使用通过组合两个单独形成的图案形成的掩模蚀刻衬底来形成集成电路的不同尺寸的特征。间距乘法用于形成第一图案的相对较小的特征以及用于形成第二图案的较大特征的常规光刻。间距倍增通过对光致抗蚀剂进行图案化，然后将该图案蚀刻成无定形碳层来实现。然后在无定形碳的侧壁上形成侧壁间隔物。去除无定形碳，留下限定第一掩模图案的侧壁间隔物。然后将底部抗反射涂层（BARC）沉积在间隔物周围以形成平坦表面，并且在BARC上形成光致抗蚀剂层。接下来通过常规光刻法将光致抗蚀剂图案化以形成第二图案，然后将其转印到BARC。通过第一图案和第二图案形成的组合图案被转印到下面的非晶硅层，并且图案经受碳带以去除BARC和光致抗蚀剂材料。然后将组合图案转移到氧化硅层，然后转移到无定形碳掩模层。具有不同尺寸特征的组合掩模图案然后通过无定形碳硬掩模层蚀刻到下面的衬底中。

5. 发明授权

US07361569B2 Methods for increasing photo-alignment margins 有权
标题翻译：增加光对准边缘的方法
公开(公告)号：US07361569B2
公开(公告)日：2008-04-22
申请号：US11496853
申请日：2006-07-31
申请人： Luan Tran , Bill Stanton
发明人： Luan Tran , Bill Stanton
IPC分类号： H01L21/76
CPC分类号： H01L21/32139 , H01L21/0337 , H01L21/0338 , H01L27/10894 , H01L27/11517 , Y10S438/942 , Y10S438/947
摘要： Methods and structures are provided for increasing alignment margins when contacting pitch multiplied interconnect lines with other conductive features in memory devices. The portions of the lines at the periphery of the memory device are formed at an angle and are widened relative to the portions of the lines in the array region of the memory device. The widened lines allow for an increased margin of error when overlaying other features, such as landing pads, on the lines. The possibility of contacting and causing electrical shorts with adjacent lines is thus minimized. In addition, forming the portions of the lines in the periphery at an angle relative to the portions of the lines in the array regions allows the peripheral portions to be widened while also allowing multiple landing pads to be densely packed at the periphery.
摘要翻译：提供了方法和结构，用于在将间距倍增的互连线与存储器件中的其它导电特征相接触时增加对准边缘。存储器件周围的线的部分形成为一角度并相对于存储器件的阵列区域中的线的部分加宽。当在线上覆盖其他特征（例如着陆垫）时，加宽的线允许增加的误差。因此，使相邻线路接触和引起电短路的可能性被最小化。此外，相对于阵列区域中的线的一部分以相对于周边的一部分线形成的部分允许周边部分被加宽，同时还允许多个着陆垫在周边被密集地包装。

6. 发明授权

US07268054B2 Methods for increasing photo-alignment margins 有权
标题翻译：增加光对准边缘的方法
公开(公告)号：US07268054B2
公开(公告)日：2007-09-11
申请号：US11497490
申请日：2006-07-31
申请人： Luan Tran , Bill Stanton
发明人： Luan Tran , Bill Stanton
IPC分类号： H01L21/76
CPC分类号： H01L21/32139 , H01L21/0337 , H01L21/0338 , H01L27/10894 , H01L27/11517 , Y10S438/942 , Y10S438/947
摘要： Methods and structures are provided for increasing alignment margins when contacting pitch multiplied interconnect lines with other conductive features in memory devices. The portions of the lines at the periphery of the memory device are formed at an angle and are widened relative to the portions of the lines in the array region of the memory device. The widened lines allow for an increased margin of error when overlaying other features, such as landing pads, on the lines. The possibility of contacting and causing electrical shorts with adjacent lines is thus minimized. In addition, forming the portions of the lines in the periphery at an angle relative to the portions of the lines in the array regions allows the peripheral portions to be widened while also allowing multiple landing pads to be densely packed at the periphery.
摘要翻译：提供了方法和结构，用于在将间距倍增的互连线与存储器件中的其它导电特征相接触时增加对准边缘。存储器件周围的线的部分形成为一角度并相对于存储器件的阵列区域中的线的部分加宽。当在线上覆盖其他特征（例如着陆垫）时，加宽的线允许增加的误差。因此，使相邻线路接触和引起电短路的可能性被最小化。此外，相对于阵列区域中的线的一部分以相对于周边的一部分线形成的部分允许周边部分被加宽，同时还允许多个着陆垫在周边被密集地包装。

7. 发明申请

US20070161251A1 PITCH REDUCED PATTERNS RELATIVE TO PHOTOLITHOGRAPHY FEATURES 失效
标题翻译：相对于光刻特征的PITCH减少图案
公开(公告)号：US20070161251A1
公开(公告)日：2007-07-12
申请号：US11681027
申请日：2007-03-01
申请人： Luan Tran , William Rericha , John Lee , Ramakanth Alapati , Sheron Honarkhah , Shuang Meng , Puneet Sharma , Jingyi Bai , Zhiping Yin , Paul Morgan , Mirzafer Abatchev , Gurtej Sandhu , D. Durcan
发明人： Luan Tran , William Rericha , John Lee , Ramakanth Alapati , Sheron Honarkhah , Shuang Meng , Puneet Sharma , Jingyi Bai , Zhiping Yin , Paul Morgan , Mirzafer Abatchev , Gurtej Sandhu , D. Durcan
IPC分类号： H01L21/302
CPC分类号： H01L21/0338 , H01L21/0337 , H01L21/3086 , H01L21/3088
摘要： Differently-sized features of an integrated circuit are formed by etching a substrate using a mask which is formed by combining two separately formed patterns. Pitch multiplication is used to form the relatively small features of the first pattern and conventional photolithography used to form the relatively large features of the second pattern. Pitch multiplication is accomplished by patterning a photoresist and then etching that pattern into an amorphous carbon layer. Sidewall spacers are then formed on the sidewalls of the amorphous carbon. The amorphous carbon is removed, leaving behind the sidewall spacers, which define the first mask pattern. A bottom anti-reflective coating (BARC) is then deposited around the spacers to form a planar surface and a photoresist layer is formed over the BARC. The photoresist is next patterned by conventional photolithography to form the second pattern, which is then is transferred to the BARC. The combined pattern made out by the first pattern and the second pattern is transferred to an underlying amorphous silicon layer and the pattern is subjected to a carbon strip to remove BARC and photoresist material. The combined pattern is then transferred to the silicon oxide layer and then to an amorphous carbon mask layer. The combined mask pattern, having features of difference sizes, is then etched into the underlying substrate through the amorphous carbon hard mask layer.
摘要翻译：通过使用通过组合两个单独形成的图案形成的掩模蚀刻衬底来形成集成电路的不同尺寸的特征。间距乘法用于形成第一图案的相对较小的特征以及用于形成第二图案的较大特征的常规光刻。间距倍增通过对光致抗蚀剂进行图案化，然后将该图案蚀刻成无定形碳层来实现。然后在无定形碳的侧壁上形成侧壁间隔物。去除无定形碳，留下限定第一掩模图案的侧壁间隔物。然后将底部抗反射涂层（BARC）沉积在间隔物周围以形成平坦表面，并且在BARC上形成光致抗蚀剂层。接下来通过常规光刻法将光致抗蚀剂图案化以形成第二图案，然后将其转印到BARC。通过第一图案和第二图案形成的组合图案被转印到下面的非晶硅层，并且图案经受碳带以去除BARC和光致抗蚀剂材料。然后将组合图案转移到氧化硅层，然后转移到无定形碳掩模层。具有不同尺寸特征的组合掩模图案然后通过无定形碳硬掩模层蚀刻到下面的衬底中。

8. 发明申请

US20070148984A1 METHOD FOR INTEGRATED CIRCUIT FABRICATION USING PITCH MULTIPLICATION 失效
标题翻译：使用PITCH MULTIPLICATION的集成电路制造方法
公开(公告)号：US20070148984A1
公开(公告)日：2007-06-28
申请号：US11683518
申请日：2007-03-08
申请人： Mirzafer Abatchev , Gurtej Sandhu , Luan Tran , William Rericha , D. Durcan
发明人： Mirzafer Abatchev , Gurtej Sandhu , Luan Tran , William Rericha , D. Durcan
IPC分类号： H01L21/302 , H01L21/461
CPC分类号： H01L21/0337 , H01L21/0332 , H01L21/0338 , H01L21/3081 , H01L21/3086 , H01L21/3088 , H01L21/31144 , H01L21/32139 , Y10S438/947 , Y10S438/95
摘要： Different sized features in the array and in the periphery of an integrated circuit are patterned on a substrate in a single step. In particular, a mixed pattern, combining two separately formed patterns, is formed on a single mask layer and then transferred to the underlying substrate. The first of the separately formed patterns is formed by pitch multiplication and the second of the separately formed patterns is formed by conventional photolithography. The first of the separately formed patterns includes lines that are below the resolution of the photolithographic process used to form the second of the separately formed patterns. These lines are made by forming a pattern on photoresist and then etching that pattern into an amorphous carbon layer. Sidewall pacers having widths less than the widths of the un-etched parts of the amorphous carbon are formed on the sidewalls of the amorphous carbon. The amorphous carbon is then removed, leaving behind the sidewall spacers as a mask pattern. Thus, the spacers form a mask having feature sizes less than the resolution of the photolithography process used to form the pattern on the photoresist. A protective material is deposited around the spacers. The spacers are further protected using a hard mask and then photoresist is formed and patterned over the hard mask. The photoresist pattern is transferred through the hard mask to the protective material. The pattern made out by the spacers and the temporary material is then transferred to an underlying amorphous carbon hard mask layer. The pattern, having features of difference sizes, is then transferred to the underlying substrate.
摘要翻译：集成电路的阵列和周边中的不同尺寸的特征在单个步骤中在衬底上图案化。特别地，组合两个单独形成的图案的混合图案形成在单个掩模层上，然后转移到下面的基底。单独形成的图案中的第一个通过间距倍增形成，并且通过常规光刻形成第二个单独形成的图案。单独形成的图案中的第一个包括低于用于形成第二个单独形成的图案的光刻工艺的分辨率的线。这些线通过在光致抗蚀剂上形成图案然后将该图案刻蚀成无定形碳层而制成。在无定形碳的侧壁上形成宽度小于无定形碳的未蚀刻部分的宽度的侧壁盘。然后去除无定形碳，留下侧壁间隔物作为掩模图案。因此，间隔物形成具有小于用于在光致抗蚀剂上形成图案的光刻工艺的分辨率的特征尺寸的掩模。保护材料沉积在间隔物周围。使用硬掩模进一步保护间隔物，然后在硬掩模上形成并图案化光致抗蚀剂。光致抗蚀剂图案通过硬掩模转印到保护材料上。然后将由间隔物和临时材料制成的图案转移到下面的无定形碳硬掩模层。具有不同尺寸特征的图案然后被转移到下面的基底。

9. 发明申请

US20070049035A1 Method of forming pitch multipled contacts 有权
标题翻译：形成螺距乘法接点的方法
公开(公告)号：US20070049035A1
公开(公告)日：2007-03-01
申请号：US11215982
申请日：2005-08-31
申请人： Luan Tran
发明人： Luan Tran
IPC分类号： H01L21/311
CPC分类号： H01L21/3088 , H01L21/0337 , H01L21/0338 , H01L21/31144 , H01L21/76805 , H01L21/76816 , H01L21/76838 , H01L27/1052 , H01L27/10888 , H01L27/11521
摘要： Methods of forming electrically conductive and/or semiconductive features for use in integrated circuits are disclosed. Various pattern transfer and etching steps can be used, in combination with pitch-reduction techniques, to create densely-packed features. The features can have a reduced pitch in one direction and a wider pitch in another direction. Conventional photo-lithography steps can be used in combination with pitch-reduction techniques to form elongate, pitch-reduced features such as bit-line contacts, for example.
摘要翻译：公开了形成用于集成电路的导电和/或半导体特征的方法。可以使用各种图案转移和蚀刻步骤，结合减音技术来产生密集包装的特征。这些特征可以在一个方向上具有减小的间距，在另一方向上可以具有较宽的间距。常规的光刻步骤可以与俯仰减小技术组合使用以形成例如细长的俯仰特征，例如位线接触。

10. 发明申请

US20060264002A1 Methods for increasing photo-alignment margins 有权
标题翻译：增加光对准边缘的方法
公开(公告)号：US20060264002A1
公开(公告)日：2006-11-23
申请号：US11497490
申请日：2006-07-31
申请人： Luan Tran , Bill Stanton
发明人： Luan Tran , Bill Stanton
IPC分类号： H01L21/76
CPC分类号： H01L21/32139 , H01L21/0337 , H01L21/0338 , H01L27/10894 , H01L27/11517 , Y10S438/942 , Y10S438/947
摘要： Methods and structures are provided for increasing alignment margins when contacting pitch multiplied interconnect lines with other conductive features in memory devices. The portions of the lines at the periphery of the memory device are formed at an angle and are widened relative to the portions of the lines in the array region of the memory device. The widened lines allow for an increased margin of error when overlaying other features, such as landing pads, on the lines. The possibility of contacting and causing electrical shorts with adjacent lines is thus minimized. In addition, forming the portions of the lines in the periphery at an angle relative to the portions of the lines in the array regions allows the peripheral portions to be widened while also allowing multiple landing pads to be densely packed at the periphery.
摘要翻译：提供了方法和结构，用于在将间距倍增的互连线与存储器件中的其它导电特征相接触时增加对准边缘。存储器件周围的线的部分形成为一角度并相对于存储器件的阵列区域中的线的部分加宽。当在线上覆盖其他特征（例如着陆垫）时，加宽的线允许增加的误差。因此，使相邻线路接触和引起电短路的可能性被最小化。此外，相对于阵列区域中的线的一部分以相对于周边部分的线形成部分，允许周边部分被加宽，同时还允许多个着陆垫在周边被密集地包装。

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