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1. 发明授权

US4962497A Building-block architecture of a multi-node circuit-and packet-switching system 失效
标题翻译：多节点电路和分组交换系统的构建块体系结构
公开(公告)号：US4962497A
公开(公告)日：1990-10-09
申请号：US410774
申请日：1989-09-21
申请人： James J. Ferenc , Louis R. Goke , Gary J. Grimes , Bryan S. Moffitt
发明人： James J. Ferenc , Louis R. Goke , Gary J. Grimes , Bryan S. Moffitt
IPC分类号： H04L12/64 , H04Q11/04
CPC分类号： H04L12/64 , H04Q11/0407
摘要： A modular, substantially infinitely-growable, multi-node switching system operates under distributed control to serve integrated circuit-switched and packet-switched traffic at the data rates appropriate for each type of traffic. The system comprises a plurality of interconnected identical switching units that form at least one communication switching node. A communication switching node is a modular building block of the system; a switching unit is a modular building block of a switching node, and hence also of the system. A plurality of communication endpoint nodes--illustratively PBXs--is connected to the one or more switching nodes for communicating with each other through the switching nodes. A plurality of communication links each connect a different one of the system's switching units to either (a) one of the communication endpoint nodes or (b) a unit of another switching node. All of the links have the same communication format. Each switching node includes a plurality of different ones of the identical switching units, and a communication medium that interconnects all of the units of the switching node to allow each unit of a node to broadcast all communications received from a connected link to all of the units of the node.
摘要翻译：模块化的，基本上无限可生长的多节点交换系统在分布式控制下操作，以适合于每种类型业务的数据速率来服务集成电路交换和分组交换业务。该系统包括形成至少一个通信交换节点的多个互连的相同的交换单元。通信交换节点是系统的模块化构建块; 切换单元是交换节点的模块化构建块，并且因此也是系统的模块化构建块。多个通信端点节点（例如PBX）连接到一个或多个交换节点，用于通过交换节点彼此通信。多个通信链路各自将系统的交换单元中的不同的一个连接到（a）通信端点节点之一或（b）另一个交换节点的单元。所有链接都具有相同的通信格式。每个交换节点包括多个不同的相同交换单元，以及通信介质，其互连交换节点的所有单元，以允许节点的每个单元将从连接的链路接收的所有通信广播到所有单元的节点。

2. 发明授权

US5146455A Wide range mixed rate TDM bus using a multiple of time slot interchange circuit switches 失效
标题翻译：宽范围混合速率TDM总线使用多个时隙交换电路交换机
公开(公告)号：US5146455A
公开(公告)日：1992-09-08
申请号：US628780
申请日：1990-12-17
申请人： Louis R. Goke , Gary J. Grimes
发明人： Louis R. Goke , Gary J. Grimes
IPC分类号： H04J3/22 , H04Q11/06
CPC分类号： H04Q11/06 , H04J3/22
摘要： A time slot converter for communicating multi-rate data on a single channel by using multiple time slots. By utilizing multiple replications of the time slot converter, any size time division switching unit such as time slot interchangers or time multiplexer switches may be assembled. The time slot converter has a plurality of switching elements and a switching element uses a time accounting arrangement that has the same overhead in assigning multiple time slots to a channel as in assigning one time slot to a channel. The switching element requires less buffer storage because each time slot has only one bit, and it is not necessary to store multiple frames. In addition, switching delay is reduced, since the delay due to buffering is always less than a frame period. Data order is maintained by using time slots for high capacity channels that are equally spaced in time and whose order is guaranteed. Also, the utlization of equally spaced time slots eliminates the need for output and input buffering to and from endpoint terminals.
摘要翻译：一种用于通过使用多个时隙在单个信道上传送多速率数据的时隙转换器。通过利用时隙转换器的多次复制，可组装诸如时隙互换器或时间复用器开关的任何尺寸的时分切换单元。时隙转换器具有多个开关元件，并且开关元件使用时间计费装置，其在将多个时隙分配给信道时具有相同的开销，就像向通道分配一个时隙一样。开关元件需要较少的缓冲存储器，因为每个时隙只有一个位，并且不需要存储多个帧。此外，由于缓冲引起的延迟总是小于帧周期，所以切换延迟减小。通过使用时间相同的高容量通道的时隙来保持数据顺序，并保证其顺序。此外，等距间隔的时隙的使用消除了对端点终端的输出和输入缓冲的需要。

3. 发明授权

US4698802A Combined circuit and packet switching system 失效
标题翻译：组合电路和分组交换系统
公开(公告)号：US4698802A
公开(公告)日：1987-10-06
申请号：US837473
申请日：1986-03-07
申请人： Louis R. Goke , Gary J. Grimes
发明人： Louis R. Goke , Gary J. Grimes
IPC分类号： H04Q11/04 , H04J3/16 , H04L12/64 , H04J3/02 , H04J3/24
CPC分类号： H04J3/1682
摘要： Apparatus for and a method of inserting circuit switch information and packetized data into different time slots of a time division multiplexed bus. A memory having a location individual to each time slot is written with information specifying whether the time slot individual to each location is to serve the circuit switch information or the packet data. The readout of each memory location during the occurrence of it's associated time slot controllably effects the application of either the circuit switch information or the packet data to the bus.
摘要翻译：将电路交换信息和分组数据插入到时分复用总线的不同时隙中的装置和方法。具有每个时隙独立的位置的存储器被写入具有指定每个位置的个别时隙是服务于电路交换信息还是分组数据的信息。每个存储器位置在其相关时隙发生期间的读出可控地影响电路交换机信息或分组数据到总线的应用。

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