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1. 发明申请

US20100225380A1 Implementing Tamper Resistant Integrated Circuit Chips 有权
标题翻译：实施防篡改集成电路芯片
公开(公告)号：US20100225380A1
公开(公告)日：2010-09-09
申请号：US12396512
申请日：2009-03-03
申请人： Louis L. Hsu , David W. Kruger , James S. Mason , Richard W. Oldrey
发明人： Louis L. Hsu , David W. Kruger , James S. Mason , Richard W. Oldrey
IPC分类号： H03K17/78
CPC分类号： H01L23/576 , H01L2224/48091 , H01L2924/1461 , H01L2924/00014 , H01L2924/00
摘要： A method and tamper resistant circuit for resisting tampering including reverse engineering in a semiconductor chip, and a design structure on which the subject circuit resides are provided. A sensing device for detecting a chip tampering state is formed with the semiconductor chip including the circuitry to be protected. A tamper resistant control signal generator is coupled to the sensing unit for generating a tamper resistant control signal responsive to a detected chip tampering state. A functional operation inhibit circuit is coupled to the tamper resistant control signal generator for inhibiting functional operation of the circuitry to be protected responsive to the tamper resistant control signal.
摘要翻译：提供一种用于抵抗篡改的方法和防篡改电路，包括半导体芯片中的逆向工程，以及设置有被摄体电路的设计结构。用于检测芯片篡改状态的感测装置由包括待保护电路的半导体芯片形成。防篡改控制信号发生器耦合到感测单元，用于响应于检测到的芯片篡改状态产生防篡改控制信号。功能操作禁止电路耦合到防篡改控制信号发生器，用于响应于防篡改控制信号而禁止要被保护的电路的功能操作。

2. 发明授权

US08089285B2 Implementing tamper resistant integrated circuit chips 有权
标题翻译：实施防篡改集成电路芯片
公开(公告)号：US08089285B2
公开(公告)日：2012-01-03
申请号：US12396512
申请日：2009-03-03
申请人： Louis L. Hsu , David W. Kruger , James S. Mason , Richard W. Oldrey
发明人： Louis L. Hsu , David W. Kruger , James S. Mason , Richard W. Oldrey
IPC分类号： G01R31/02 , G01R31/26 , G06F12/14 , G06F7/04
CPC分类号： H01L23/576 , H01L2224/48091 , H01L2924/1461 , H01L2924/00014 , H01L2924/00
摘要： A method and tamper resistant circuit for resisting tampering including reverse engineering in a semiconductor chip, and a design structure on which the subject circuit resides are provided. A sensing device for detecting a chip tampering state is formed with the semiconductor chip including the circuitry to be protected. A tamper resistant control signal generator is coupled to the sensing unit for generating a tamper resistant control signal responsive to a detected chip tampering state. A functional operation inhibit circuit is coupled to the tamper resistant control signal generator for inhibiting functional operation of the circuitry to be protected responsive to the tamper resistant control signal.
摘要翻译：提供一种用于抵抗篡改的方法和防篡改电路，包括半导体芯片中的逆向工程，以及设置有被摄体电路的设计结构。用于检测芯片篡改状态的感测装置由包括待保护电路的半导体芯片形成。防篡改控制信号发生器耦合到感测单元，用于响应于检测到的芯片篡改状态产生防篡改控制信号。功能操作禁止电路耦合到防篡改控制信号发生器，用于响应于防篡改控制信号而禁止要被保护的电路的功能操作。

3. 发明授权

US5373109A Electrical cable having flat, flexible, multiple conductor sections 失效
标题翻译：电缆具有扁平，柔性，多导体部分
公开(公告)号：US5373109A
公开(公告)日：1994-12-13
申请号：US995494
申请日：1992-12-23
申请人： Straty N. Argyrakis , Richard W. Oldrey , Eugene E. Steele
发明人： Straty N. Argyrakis , Richard W. Oldrey , Eugene E. Steele
IPC分类号： H01B7/08
CPC分类号： H01R12/774 , H01R12/78
摘要： An electrical cable having a plurality of flat, flexible cable sections. Each section has flat, electrically conductive ground layers on at least the top and bottom surfaces thereof, and a plurality of flat, electrically conductive signal conductors between the ground layers. A plurality of dielectric layers separates the signal conductors from each other and from the ground layers. Each signal conductor includes an exposed surface extending a short distance from the end of the conductor along the length of each section. Adjacent cable sections are positioned relative to each other so that the exposed surfaces of corresponding signal conductors face each other. A plurality of connector assemblies is interposed between adjacent cable sections for electrically conducting the exposed surfaces of the corresponding signal conductors. Retaining means are provided for securing the ends of adjacent cable sections and connector assemblies in electrical contact with each other. The adjacent cable sections terminate at the retaining means and reverse direction to create an accordian type configuration for the cable.
摘要翻译：一种具有多个扁平柔性电缆部分的电缆。每个部分至少在其顶表面和底表面上具有平坦的导电接地层，以及在接地层之间的多个平坦的，导电的信号导体。多个电介质层将信号导体与接地层分开。每个信号导体包括沿着每个部分的长度从导体的端部延伸一短距离的暴露表面。相邻的电缆部分相对于彼此定位，使得相应的信号导体的暴露的表面彼此面对。多个连接器组件插入相邻的电缆部分之间，用于导电相应信号导体的暴露表面。提供保持装置用于固定相邻电缆部分和连接器组件的端部彼此电接触。相邻的电缆段终止于保持装置和反向，以产生用于电缆的协调式配置。

4. 发明申请

US20080272474A1 APPARATUS FOR INTEGRATED CIRCUIT COOLING DURING TESTING AND IMAGE BASED ANALYSIS 审中-公开
标题翻译：用于测试和图像分析期间的集成电路冷却的设备
公开(公告)号：US20080272474A1
公开(公告)日：2008-11-06
申请号：US12175095
申请日：2008-07-17
申请人： Patrick J. McGinnis , Darrell L. Miles , Richard W. Oldrey , John D. Sylvestri , Manuel J. Villalobos
发明人： Patrick J. McGinnis , Darrell L. Miles , Richard W. Oldrey , John D. Sylvestri , Manuel J. Villalobos
IPC分类号： H01L23/473
CPC分类号： G01R31/2891 , G01R31/311
摘要： An apparatus for implementing integrated circuit cooling during testing and image-based analysis thereof includes a lid configured to define a cavity surrounding an integrated circuit die, the die mounted to a module substrate. One or more fluid passages are defined within the lid, wherein the passages facilitate the flow of a cooling liquid through said cavity and over the integrated circuit die, and a transparent window is formed within the lid so as to facilitate viewing of the integrated circuit die.
摘要翻译：一种用于在测试期间实现集成电路冷却的装置和其基于图像的分析，其包括：盖，其被配置为限定集成电路管芯周围的空腔，所述管芯安装到模块基板。一个或多个流体通道限定在盖内，其中通道有助于冷却液体流过所述空腔并在集成电路管芯上流动，并且在盖内形成透明窗口，以便于观察集成电路管芯。

5. 发明授权

US06894522B2 Specific site backside underlaying and micromasking method for electrical characterization of semiconductor devices 失效
标题翻译：半导体器件的电气特性的具体现场背面底层和微掩模方法
公开(公告)号：US06894522B2
公开(公告)日：2005-05-17
申请号：US10605530
申请日：2003-10-06
申请人： Barbara A. Averill , Terence Kane , Darrell L. Miles , Richard W. Oldrey , John D. Sylvestri
发明人： Barbara A. Averill , Terence Kane , Darrell L. Miles , Richard W. Oldrey , John D. Sylvestri
IPC分类号： G01N1/32 , G01R31/28 , G01R31/26
CPC分类号： G01R31/2886 , G01N1/32 , G01R31/2898
摘要： A method for implementing backside probing of a semiconductor device includes isolating an identified defect area on a backside of the semiconductor device, and milling the identified defect area to an initial depth. Edges of the identified defect area are masked, wherein unmasked semiconductor material, beginning at the initial depth, is etched for a plurality of timed intervals until one or more active devices are reached. The one or more active devices are electrically probed.
摘要翻译：用于实现半导体器件的背面探测的方法包括隔离半导体器件的背面上的识别的缺陷区域，以及将所识别的缺陷区域研磨到初始深度。所识别的缺陷区域的边缘被掩蔽，其中从初始深度开始的未屏蔽半导体材料被蚀刻多个定时间隔，直到达到一个或多个有源器件。一个或多个有源器件被电探测。

6. 发明授权

US07112983B2 Apparatus and method for single die backside probing of semiconductor devices 有权
标题翻译：半导体器件单模背面探测的装置和方法
公开(公告)号：US07112983B2
公开(公告)日：2006-09-26
申请号：US10904435
申请日：2004-11-10
申请人： Patrick J. McGinnis , Darrell L. Miles , Richard W. Oldrey , John D. Sylvestri , Manuel J. Villalobos
发明人： Patrick J. McGinnis , Darrell L. Miles , Richard W. Oldrey , John D. Sylvestri , Manuel J. Villalobos
IPC分类号： G01R31/26
CPC分类号： G01R31/2886 , G01R1/0408 , G01R31/311
摘要： An apparatus for facilitating single die backside probing of semiconductor devices includes a chip holder configured for receiving a single integrated circuit die attached thereto, the chip holder maintained in flexible engagement in an X-Y orientation with respect to a lift plate. A lift ring is coupled to the lift plate, the lift ring configured to facilitate adjustment of the lift plate and the chip holder in a Z-direction.
摘要翻译：用于促进半导体器件的单模背面探测的装置包括芯片保持器，其构造成用于接收附接到其上的单个集成电路管芯，所述芯片保持器相对于升降板以X-Y取向保持柔性接合。提升环联接到提升板，提升环构造成便于在Z方向上调节提升板和芯片保持器。

7. 发明授权

US07269029B2 Rapid fire test board 失效
标题翻译：快速测试板
公开(公告)号：US07269029B2
公开(公告)日：2007-09-11
申请号：US10904416
申请日：2004-11-09
申请人： Richard W. Oldrey
发明人： Richard W. Oldrey
IPC分类号： H05K1/14
CPC分类号： G01R31/31926 , G01R31/31905 , H05K1/0268 , H05K3/429 , H05K2201/09309 , H05K2201/10689 , H05K2203/0242
摘要： A test board for testing a packaged integrated circuit has a set of contacts matching counterpart contacts on a socket. The contacts are each connected to a first voltage plane containing power, a second voltage plane carrying ground, and a set of terminals that will be connected to a tester system. The number of terminals necessary to operate the circuit is identified, both power terminal and signal-carrying terminals to the affected part of the circuit, and two of the three connections to the contacts are severed; e.g. the terminal carrying signals is disconnected from the power and ground. The disconnect from the voltage planes may be performed by an automated milling machine in a short time, providing much faster turnaround than a method that forms a custom-made board.
摘要翻译：用于测试封装集成电路的测试板具有一组与插座上的对应触点匹配的触点。触点各自连接到包含电力的第一电压平面，承载地面的第二电压平面以及将连接到测试器系统的一组端子。识别操作电路所需的端子数量，电源端子和信号承载端子到电路的受影响部分，并且三个到触点的连接中的两个被切断; 例如终端承载信号与电源和接地断开。与电压平面的断开可以通过自动铣床在短时间内进行，提供比形成定制板的方法更快的周转。

8. 发明授权

US5380955A Device for passing a member through a sealed chamber wall 失效
标题翻译：用于使构件通过密封室壁的装置
公开(公告)号：US5380955A
公开(公告)日：1995-01-10
申请号：US987932
申请日：1992-12-08
申请人： Straty N. Argyrakis , Willard S. Harris , Richard W. Oldrey , Edward J. Ossolinski
发明人： Straty N. Argyrakis , Willard S. Harris , Richard W. Oldrey , Edward J. Ossolinski
IPC分类号： H01B17/26 , H05K9/00
CPC分类号： H05K9/0018 , H01B17/26
摘要： A device is provided for passing a member through the wall of a sealed chamber. The member has an outer surface having a portion thereof which is substantially formed of metal. A flange has an opening therein which surrounds and is spaced from the metal portion of the member. A solder member completely fills the space between the flange opening and the metal portion of the member for creating a seal therebetween which is capable of maintaining a high pressure differential between opposite sides of the sealed chamber wall. The member is preferably a flat, multi-conductor electrical cable having thin, flat, copper shielding layers on the top and bottom thereof. The metal portion preferably includes a wedge-shaped copper member which surrounds the electrical cable and is intricately affixed to the shielding layers. The solder member is preferably a solder compound comprising 52 percent indium and 48 percent tin.
摘要翻译：提供了用于使构件穿过密封室的壁的装置。该构件具有其表面基本上由金属形成的一部分。凸缘在其中具有围绕并与构件的金属部分间隔开的开口。焊料构件完全填充凸缘开口和构件的金属部分之间的空间，用于在其之间形成密封件，其能够保持密封室壁的相对侧之间的高压差。该构件优选地是在其顶部和底部上具有薄的，平坦的铜屏蔽层的扁平多导体电缆。金属部分优选地包括楔形铜构件，其围绕电缆并且复杂地固定到屏蔽层。焊料构件优选为包含52％铟和48％锡的焊料化合物。

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