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1. 发明申请

US20050123017A1 External cavity tunable laser system formed MEMS corner mirror 失效
标题翻译：外腔可调谐激光系统形成MEMS角镜
公开(公告)号：US20050123017A1
公开(公告)日：2005-06-09
申请号：US10977044
申请日：2004-10-29
申请人： Long-Sun Huang , Chao-Sen Chang , Ta-Shun Chu , Son-Nan Chen
发明人： Long-Sun Huang , Chao-Sen Chang , Ta-Shun Chu , Son-Nan Chen
IPC分类号： H01S3/00 , H01S3/081 , H01S5/14
CPC分类号： H01S5/143 , H01S3/105 , H01S5/02284 , H01S5/1096
摘要： A tunable laser system is provided. The tunable laser system includes a light source, a grating, a corner mirror array, and a receiver. In which, the light source emits a beam, and the grating is located in front of the light source for reflecting the beam to form a first reflective beam. Also, the corner mirror array is located in front of the grating for receiving the first reflective beam and forms a second reflective beam accordingly. In addition, the receiver is used to receive a third reflective beam formed from reflecting the second reflective beam through the grating.
摘要翻译：提供可调激光系统。可调谐激光系统包括光源，光栅，角镜阵列和接收器。其中，光源发射光束，并且光栅位于光源的前面，用于反射光束以形成第一反射光束。此外，角镜阵列位于光栅的前面，用于接收第一反射光束并相应地形成第二反射光束。此外，接收器用于接收通过将第二反射光束反射通过光栅而形成的第三反射光束。

2. 发明授权

US07605970B2 External cavity tunable laser system formed from MEMS corner mirror 失效
标题翻译：由MEMS角镜形成的外腔可调谐激光系统
公开(公告)号：US07605970B2
公开(公告)日：2009-10-20
申请号：US10977044
申请日：2004-10-29
申请人： Long-Sun Huang , Chao-Sen Chang , Ta-Shun Chu , Son-Nan Chen
发明人： Long-Sun Huang , Chao-Sen Chang , Ta-Shun Chu , Son-Nan Chen
IPC分类号： G02B26/00
CPC分类号： H01S5/143 , H01S3/105 , H01S5/02284 , H01S5/1096
摘要： A tunable laser system is provided. The tunable laser system includes a light source, a grating, a corner mirror array, and a receiver. In which, the light source emits a beam, and the grating is located in front of the light source for reflecting the beam to form a first reflective beam. Also, the corner mirror array is located in front of the grating for receiving the first reflective beam and forms a second reflective beam accordingly. In addition, the receiver is used to receive a third reflective beam formed from reflecting the second reflective beam through the grating.
摘要翻译：提供可调激光系统。可调谐激光系统包括光源，光栅，角镜阵列和接收器。其中，光源发射光束，并且光栅位于光源的前面，用于反射光束以形成第一反射光束。此外，角镜阵列位于光栅的前面，用于接收第一反射光束并相应地形成第二反射光束。此外，接收器用于接收通过将第二反射光束反射通过光栅而形成的第三反射光束。

3. 发明授权

US10128860B1 High speed SAR ADC using comparator output triggered binary-search timing scheme and bit-dependent DAC settling 有权
公开(公告)号：US10128860B1
公开(公告)日：2018-11-13
申请号：US15653156
申请日：2017-07-18
申请人： Yuan-Ju Chao , Ta-Shun Chu
发明人： Yuan-Ju Chao , Ta-Shun Chu
IPC分类号： H03M1/06 , H03K5/24 , H03M1/10 , H03M1/12 , H03M1/00 , H03K5/00
CPC分类号： H03K5/24 , H03K2005/00058 , H03M1/00 , H03M1/06 , H03M1/1071 , H03M1/12 , H03M1/125 , H03M1/468
摘要： A method of increasing SAR ADC conversion rate and reducing power consumption by employing a new timing scheme and minimizing timing delay for each bit-test during binary-search process. The high frequency clock input requirement is eliminated and higher speed rate can be achieved in SAR ADC.

4. 发明授权

US10014874B1 System and method of minimizing differential non-linearity (DNL) for high resolution current steering DAC 有权
公开(公告)号：US10014874B1
公开(公告)日：2018-07-03
申请号：US15792563
申请日：2017-10-24
申请人： Yuan-Ju Chao , Ta-Shun Chu
发明人： Yuan-Ju Chao , Ta-Shun Chu
IPC分类号： H03M1/66 , H03M1/06 , H03M1/68
CPC分类号： H03M1/0612 , H03M1/662 , H03M1/687 , H03M1/742
摘要： A current steering converter fabricated using a predetermined integrated circuit technology includes a unary portion having one or more current sources and a binary portion including a plurality of switches controlled by a decoder, the switches coupled to a converter output; and a plurality of devices commonly connected at a first end and coupled to each respective switch at a second end, wherein each device size comprises (W/L)*M, where W/L is a width and length of the device and M is an integer representing multiple number.

5. 发明授权

US09866236B1 Appapatus and method for fast conversion, compact, ultra low power, wide supply range auxiliary digital to analog converters 有权
公开(公告)号：US09866236B1
公开(公告)日：2018-01-09
申请号：US15414516
申请日：2017-01-24
申请人： Yuan-Ju Chao , Ta-Shun Chu
发明人： Yuan-Ju Chao , Ta-Shun Chu
IPC分类号： H03M1/66 , H03M1/78 , H03M1/38
CPC分类号： H03M1/785 , H03M1/38 , H03M1/802
摘要： A data converter includes a single-end capacitive digital to analog converter (DAC); a transconductance (GM) buffer having an output, a positive input coupled to the DAC and a negative input coupled to the output; a resistor and a capacitor load in parallel coupled to the output at one terminal and to ground at the other terminal. The developed architecture of comprising single end capacitive DAC and GM-based buffer provides fast conversion rate, low current consumption, small silicon area and wide supply range for general-purpose auxiliary DAC applications.

6. 发明授权

US09774337B1 High speed SAR ADC using comparator output triggered binary-search timing scheme and bit-dependent DAC settling 有权
公开(公告)号：US09774337B1
公开(公告)日：2017-09-26
申请号：US15594260
申请日：2017-05-12
申请人： Yuan-Ju Chao , Ta-Shun Chu
发明人： Yuan-Ju Chao , Ta-Shun Chu
IPC分类号： H03M1/06 , H03M1/10 , H03K5/24 , H03K5/00 , H03M1/00 , H03M1/12
CPC分类号： H03M1/06 , H03K5/24 , H03K2005/00058 , H03M1/00 , H03M1/1071 , H03M1/12 , H03M1/125 , H03M1/468
摘要： A method of increasing SAR ADC conversion rate and reducing power consumption by employing a new timing scheme and minimizing timing delay for each bit-test during binary-search process. The high frequency clock input requirement is eliminated and higher speed rate can be achieved in SAR ADC.

7. 发明授权

US08203484B2 Path-sharing transceiver architecture for antenna arrays 有权
标题翻译：天线阵列的路径共享收发器架构
公开(公告)号：US08203484B2
公开(公告)日：2012-06-19
申请号：US12029253
申请日：2008-02-11
申请人： Ta-Shun Chu , Hossein Hashemi
发明人： Ta-Shun Chu , Hossein Hashemi
IPC分类号： H01Q3/22
CPC分类号： H01Q3/2682
摘要： A path sharing transceiver array architecture is disclosed. A plurality of channels are linked to antennas of an array for transmitting and receiving wireless signals that are offset in one of phase or time relative to one another. Each channel is associated with a delay element. In the receiving case, an offset signal is received at a first channel, processed, and shifted by a first delay element. The resulting signal is combined with the processed signal of a second, adjacent channel where a phase or time delayed signal is received. The combined signal is then shifted by a second delay element to produce a net signal. The first delay element is used to generate a shifted signal for both the first and second channel. The architecture can be extended to another number of channels.
摘要翻译：公开了路径共享收发器阵列架构。多个信道被链接到阵列的天线，用于发送和接收相对于彼此之一相位或时间偏移的无线信号。每个通道与延迟元件相关联。在接收情况下，偏移信号在第一信道被接收，被第一延迟元件处理和移位。所得信号与接收相位或时间延迟信号的第二相邻信道的处理信号相组合。然后组合的信号被第二延迟元件移位以产生净信号。第一延迟元件用于产生用于第一和第二通道的移位信号。该架构可以扩展到另外数量的频道。

8. 发明授权

US09843336B1 System and method of minimizing differential non-linearity (DNL) for high resolution current steering DAC 有权
公开(公告)号：US09843336B1
公开(公告)日：2017-12-12
申请号：US15494533
申请日：2017-04-23
申请人： Yuan-Ju Chao , Ta-Shun Chu
发明人： Yuan-Ju Chao , Ta-Shun Chu
IPC分类号： H03M1/66 , H03M1/06 , H03M1/68
CPC分类号： H03M1/0612 , H03M1/662 , H03M1/687 , H03M1/742
摘要： A current steering converter fabricated using a predetermined integrated circuit technology includes a unary portion having one or more current sources and a binary portion including a plurality of switches controlled by a decoder, the switches coupled to a converter output; and a plurality of devices commonly connected at a first end and coupled to each respective switch at a second end, wherein each device size comprises (W/L)*M, where W/L is a width and length of the device and M is an integer representing multiple number.

9. 发明授权

US09621180B1 Apparatus and method for fast conversion, compact, ultra low power, wide supply range auxiliary digital to analog converters 有权
公开(公告)号：US09621180B1
公开(公告)日：2017-04-11
申请号：US15247651
申请日：2016-08-25
申请人： Yuan-Ju Chao , Ta-Shun Chu
发明人： Yuan-Ju Chao , Ta-Shun Chu
IPC分类号： H03M1/66 , H03M1/78 , H03M1/38
CPC分类号： H03M1/785 , H03M1/38 , H03M1/802
摘要： A data converter includes a single-end capacitive digital to analog converter (DAC); a transconductance (GM) buffer having an output, a positive input coupled to the DAC and a negative input coupled to the output; a resistor and a capacitor load in parallel coupled to the output at one terminal and to ground at the other terminal. The developed architecture of comprising single end capacitive DAC and GM-based buffer provides fast conversion rate, low current consumption, small silicon area and wide supply range for general-purpose auxiliary DAC applications.

10. 发明授权

US09979382B1 Programmable duty-cycle low jitter differential clock buffer 有权
公开(公告)号：US09979382B1
公开(公告)日：2018-05-22
申请号：US15451113
申请日：2017-03-06
申请人： Yuan-Ju Chao , Ta-Shun Chu
发明人： Yuan-Ju Chao , Ta-Shun Chu
IPC分类号： H03K5/156 , H03K5/19 , G11C27/02
CPC分类号： H03K5/1565 , H03K5/19
摘要： A method of detecting clock duty cycle and adjusting clock duty cycle to achieve a clock with low jitters, low noise, high common mode rejection and high power supply rejection for sampling circuit. Adjusting the duty cycle of the sampling clock can enhance data converter's performance.

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