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1. 发明申请

US20060223323A1 METHOD OF FORMING AN INTERCONNECT STRUCTURE 失效
标题翻译：形成互连结构的方法
公开(公告)号：US20060223323A1
公开(公告)日：2006-10-05
申请号：US11424359
申请日：2006-06-15
申请人： Liang-Yuh Chen , Daniel Carl , Israel Beinglass
发明人： Liang-Yuh Chen , Daniel Carl , Israel Beinglass
IPC分类号： H01L21/311
CPC分类号： C23C16/45589 , C23C14/046 , C23C16/045 , H01L21/2855 , H01L21/28556 , H01L21/76843 , H01L21/76865
摘要： A method of layer formation on a substrate with high aspect ratio features is disclosed. The layer is formed from a gas mixture comprising one or more process gases and one or more etch species. The one or more process gases react to deposit a material layer on the substrate. In conjunction with the material layer deposition, the etch species selectively remove portions of the deposited material layer adjacent to high aspect ratio feature openings, filling such features in a void-free and/or seam-free manner. The material layer may be deposited on the substrate using physical vapor deposition (PVD) and/or chemical vapor deposition (CVD) techniques.
摘要翻译：公开了一种在具有高纵横比特征的基底上形成层的方法。该层由包含一种或多种工艺气体和一种或多种蚀刻物质的气体混合物形成。一种或多种工艺气体反应以在衬底上沉积材料层。结合材料层沉积，蚀刻物质选择性地去除与高纵横比特征开口相邻的沉积材料层的部分，以无空隙和/或无缝隙的方式填充这些特征。材料层可以使用物理气相沉积（PVD）和/或化学气相沉积（CVD）技术沉积在衬底上。

2. 发明申请

US20060223322A1 METHOD OF FORMING A TRENCH STRUCTURE 失效
标题翻译：形成TRENCH结构的方法
公开(公告)号：US20060223322A1
公开(公告)日：2006-10-05
申请号：US11424351
申请日：2006-06-15
申请人： Liang-Yuh Chen , Daniel Carl , Israel Beinglass
发明人： Liang-Yuh Chen , Daniel Carl , Israel Beinglass
IPC分类号： H01L21/311
CPC分类号： C23C16/45589 , C23C14/046 , C23C16/045 , H01L21/2855 , H01L21/28556 , H01L21/76843 , H01L21/76865
摘要： A method of layer formation on a substrate with high aspect ratio features is disclosed. The layer is formed from a gas mixture comprising one or more process gases and one or more etch species. The one or more process gases react to deposit a material layer on the substrate. In conjunction with the material layer deposition, the etch species selectively remove portions of the deposited material layer adjacent to high aspect ratio feature openings, filling such features in a void-free and/or seam-free manner. The material layer may be deposited on the substrate using physical vapor deposition (PVD) and/or chemical vapor deposition (CVD) techniques.
摘要翻译：公开了一种在具有高纵横比特征的基底上形成层的方法。该层由包含一种或多种工艺气体和一种或多种蚀刻物质的气体混合物形成。一种或多种工艺气体反应以在衬底上沉积材料层。结合材料层沉积，蚀刻物质选择性地去除与高纵横比特征开口相邻的沉积材料层的部分，以无空隙和/或无缝隙的方式填充这些特征。材料层可以使用物理气相沉积（PVD）和/或化学气相沉积（CVD）技术沉积在衬底上。

3. 发明授权

US07427568B2 Method of forming an interconnect structure 失效
标题翻译：形成互连结构的方法
公开(公告)号：US07427568B2
公开(公告)日：2008-09-23
申请号：US11424359
申请日：2006-06-15
申请人： Liang-Yuh Chen , Daniel A. Carl , Israel Beinglass
发明人： Liang-Yuh Chen , Daniel A. Carl , Israel Beinglass
IPC分类号： H01L21/311 , C23C14/34
CPC分类号： C23C16/45589 , C23C14/046 , C23C16/045 , H01L21/2855 , H01L21/28556 , H01L21/76843 , H01L21/76865
摘要： A method of layer formation on a substrate with high aspect ratio features is disclosed. The layer is formed from a gas mixture comprising one or more process gases and one or more etch species. The one or more process gases react to deposit a material layer on the substrate. In conjunction with the material layer deposition, the etch species selectively remove portions of the deposited material layer adjacent to high aspect ratio feature openings, filling such features in a void-free and/or seam-free manner. The material layer may be deposited on the substrate using physical vapor deposition (PVD) and/or chemical vapor deposition (CVD) techniques.
摘要翻译：公开了一种在具有高纵横比特征的基底上形成层的方法。该层由包含一种或多种工艺气体和一种或多种蚀刻物质的气体混合物形成。一种或多种工艺气体反应以在衬底上沉积材料层。结合材料层沉积，蚀刻物质选择性地去除与高纵横比特征开口相邻的沉积材料层的部分，以无空隙和/或无缝隙的方式填充这些特征。材料层可以使用物理气相沉积（PVD）和/或化学气相沉积（CVD）技术沉积在衬底上。

4. 发明授权

US07115516B2 Method of depositing a material layer 失效
标题翻译：沉积材料层的方法
公开(公告)号：US07115516B2
公开(公告)日：2006-10-03
申请号：US09974535
申请日：2001-10-09
申请人： Liang-Yuh Chen , Daniel A. Carl , Israel Beinglass
发明人： Liang-Yuh Chen , Daniel A. Carl , Israel Beinglass
IPC分类号： H01L21/4763
CPC分类号： C23C16/45589 , C23C14/046 , C23C16/045 , H01L21/2855 , H01L21/28556 , H01L21/76843 , H01L21/76865
摘要： A method of layer formation on a substrate with high aspect ratio features is disclosed. The layer is formed from a gas mixture comprising one or more process gases and one or more etch species. The one or more process gases react to deposit a material layer on the substrate. In conjunction with the material layer deposition, the etch species selectively remove portions of the deposited material layer adjacent to high aspect ratio feature openings, filling such features in a void-free and/or seam-free manner. The material layer may be deposited on the substrate using physical vapor deposition (PVD) and/or chemical vapor deposition (CVD) techniques.
摘要翻译：公开了一种在具有高纵横比特征的基底上形成层的方法。该层由包含一种或多种工艺气体和一种或多种蚀刻物质的气体混合物形成。一种或多种工艺气体反应以在衬底上沉积材料层。结合材料层沉积，蚀刻物质选择性地去除与高纵横比特征开口相邻的沉积材料层的部分，以无空隙和/或无缝隙的方式填充这些特征。材料层可以使用物理气相沉积（PVD）和/或化学气相沉积（CVD）技术沉积在衬底上。

5. 发明授权

US06169030A Metallization process and method 失效
标题翻译：金属化过程和方法
公开(公告)号：US06169030A
公开(公告)日：2001-01-02
申请号：US09007233
申请日：1998-01-14
申请人： Mehul B. Naik , Ted Guo , Liang-Yuh Chen , Roderick Craig Mosely , Israel Beinglass
发明人： Mehul B. Naik , Ted Guo , Liang-Yuh Chen , Roderick Craig Mosely , Israel Beinglass
IPC分类号： H01L2144
CPC分类号： C23C14/32 , C23C14/025 , C23C14/046 , H01L21/2855 , H01L21/76877
摘要： The invention generally provides an improved process for providing uniform step coverage on a substrate and planarization of metal layers to form continuous, void-free interconnections in high aspect ratio, sub-half micron applications. The invention provides a multi-step PVD process in which the plasma power is varied for each of the steps to obtain favorable fill characteristics as well as good reflectivity, morphology and throughput. The initial plasma powers are relatively low to ensure good, void-free filling of the aperture and, then, the plasma powers are increased to obtain the desired reflectivity and morphology characteristics. The invention provides an aperture filling process comprising physical vapor depositing a metal over the substrate and varying the plasma power during the physical vapor deposition. Preferably, the plasma power is varied from a first discrete low plasma power to a second discrete high plasma power. Even more preferably, the plasma power is varied from a first discrete low plasma power to a second discrete low plasma power to a third discrete high plasma power.
摘要翻译：本发明通常提供了一种改进的方法，用于在衬底上提供均匀的台阶覆盖和金属层的平坦化，以在高纵横比，半微米应用中形成连续的无空隙互连。本发明提供了一种多步骤PVD工艺，其中等离子体功率对于每个步骤而言是变化的，以获得良好的填充特性以及良好的反射率，形态和产量。初始等离子体功率相对较低，以确保孔的良好的无空隙填充，然后增加等离子体功率以获得期望的反射率和形态特征。本发明提供一种孔填充方法，其包括在物理气相沉积中物理气相沉积衬底上的金属并改变等离子体功率。优选地，等离子体功率从第一离散低等离子体功率变化到第二离散高等离子体功率。更优选地，等离子体功率从第一离散低等离子体功率变化到第二离散低等离子体功率到第三离散高等离子体功率。

6. 发明授权

US07772121B2 Method of forming a trench structure 失效
标题翻译：形成沟槽结构的方法
公开(公告)号：US07772121B2
公开(公告)日：2010-08-10
申请号：US11424351
申请日：2006-06-15
申请人： Liang-Yuh Chen , Daniel A. Carl , Israel Beinglass
发明人： Liang-Yuh Chen , Daniel A. Carl , Israel Beinglass
IPC分类号： H01L21/00
CPC分类号： C23C16/45589 , C23C14/046 , C23C16/045 , H01L21/2855 , H01L21/28556 , H01L21/76843 , H01L21/76865
摘要： A method of layer formation on a substrate with high aspect ratio features is disclosed. The layer is formed from a gas mixture comprising one or more process gases and one or more etch species. The one or more process gases react to deposit a material layer on the substrate. In conjunction with the material layer deposition, the etch species selectively remove portions of the deposited material layer adjacent to high aspect ratio feature openings, filling such features in a void-free and/or seam-free manner. The material layer may be deposited on the substrate using physical vapor deposition (PVD) and/or chemical vapor deposition (CVD) techniques.
摘要翻译：公开了一种在具有高纵横比特征的基底上形成层的方法。该层由包含一种或多种工艺气体和一种或多种蚀刻物质的气体混合物形成。一种或多种工艺气体反应以在衬底上沉积材料层。结合材料层沉积，蚀刻物质选择性地去除与高纵横比特征开口相邻的沉积材料层的部分，以无空隙和/或无缝隙的方式填充这些特征。材料层可以使用物理气相沉积（PVD）和/或化学气相沉积（CVD）技术沉积在衬底上。

7. 发明授权

US08664042B2 Method for fabrication of configurable systems 有权
标题翻译：可配置系统的制造方法
公开(公告)号：US08664042B2
公开(公告)日：2014-03-04
申请号：US13471009
申请日：2012-05-14
申请人： Zvi Or-Bach , Deepak C. Sekar , Brian Cronquist , Israel Beinglass , Jan Lodewijk de Jong
发明人： Zvi Or-Bach , Deepak C. Sekar , Brian Cronquist , Israel Beinglass , Jan Lodewijk de Jong
IPC分类号： H01L21/00
CPC分类号： H01L21/76254 , H01L21/8221 , H01L21/84 , H01L23/36 , H01L23/481 , H01L24/48 , H01L25/0657 , H01L27/0688 , H01L27/092 , H01L27/105 , H01L27/11 , H01L27/1104 , H01L2224/16145 , H01L2224/16225 , H01L2224/32145 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/73204 , H01L2224/73265 , H01L2924/00014 , H01L2924/01019 , H01L2924/01066 , H01L2924/01322 , H01L2924/10253 , H01L2924/12032 , H01L2924/12042 , H01L2924/1301 , H01L2924/1305 , H01L2924/13062 , H01L2924/13091 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2924/3011 , H03K19/177 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A method to construct configurable systems, the method including: providing a first configurable system including a first die and a second die, where the connections between the first die and the second die include through-silicon-via (“TSV”), where the first die is diced from a first wafer using first dice lines; providing a second configurable system including a third die and a fourth die, where the connections between the third die and the fourth die include through-silicon-via (“TSV”), where the third die is diced from a third wafer using third dice lines; and processing the first wafer and the third wafer utilizing at least 20 masks that are the same; where the first dice lines are substantially different than the third dice lines, and where the second die includes a configurable I/O to connect the first configurable system to external devices.
摘要翻译：一种构建可配置系统的方法，所述方法包括：提供包括第一管芯和第二管芯的第一可配置系统，其中第一管芯和第二管芯之间的连接包括穿硅通孔（“TSV”），其中使用第一骰子线从第一晶片切下第一芯片; 提供包括第三管芯和第四管芯的第二可配置系统，其中第三管芯和第四管芯之间的连接包括穿硅通孔（“TSV”），其中使用第三管芯从第三晶片切割第三管芯线条以及使用相同的至少20个掩模来处理所述第一晶片和所述第三晶片; 其中第一骰子线与第三骰子线基本上不同，并且其中第二骰子包括用于将第一可配置系统连接到外部装置的可配置I / O。

8. 发明授权

US08395191B2 Semiconductor device and structure 有权
标题翻译：半导体器件及结构
公开(公告)号：US08395191B2
公开(公告)日：2013-03-12
申请号：US12900379
申请日：2010-10-07
申请人： Zvi Or-Bach , Brian Cronquist , Israel Beinglass , Jan Lodewijk de Jong , Deepak C. Sekar , Zeev Wurman
发明人： Zvi Or-Bach , Brian Cronquist , Israel Beinglass , Jan Lodewijk de Jong , Deepak C. Sekar , Zeev Wurman
IPC分类号： H01L21/336 , H01L21/8234 , H01L21/76 , H01L29/76 , H01L29/772 , H01L25/065
CPC分类号： H01L27/0688 , G03F9/7076 , G03F9/7084 , H01L21/268 , H01L21/76254 , H01L21/76898 , H01L21/8221 , H01L21/823871 , H01L21/84 , H01L23/367 , H01L23/481 , H01L23/5226 , H01L23/528 , H01L23/53214 , H01L23/53228 , H01L23/544 , H01L24/73 , H01L27/0207 , H01L27/088 , H01L27/092 , H01L27/105 , H01L27/10876 , H01L27/10894 , H01L27/10897 , H01L27/11 , H01L27/1108 , H01L27/112 , H01L27/11551 , H01L27/11578 , H01L27/11807 , H01L27/11898 , H01L27/1203 , H01L29/42392 , H01L29/458 , H01L29/66272 , H01L29/66545 , H01L29/66621 , H01L29/66848 , H01L29/66901 , H01L29/732 , H01L29/78639 , H01L29/78642 , H01L29/78645 , H01L29/808 , H01L29/812 , H01L2223/5442 , H01L2223/54426 , H01L2223/54453 , H01L2224/16145 , H01L2224/16225 , H01L2224/32145 , H01L2224/32225 , H01L2224/45124 , H01L2224/45147 , H01L2224/48091 , H01L2224/48227 , H01L2224/73204 , H01L2224/73253 , H01L2224/73265 , H01L2924/00011 , H01L2924/10253 , H01L2924/12032 , H01L2924/1301 , H01L2924/1305 , H01L2924/13062 , H01L2924/13091 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2924/3011 , H01L2924/3025 , H01L2924/00014 , H01L2924/00 , H01L2224/80001 , H01L2924/00012 , H01L2924/01015
摘要： A semiconductor device including a first single crystal layer with first transistors and a first alignment mark; at least one metal layer overlying the first single crystal layer, wherein the at least one metal layer includes copper or aluminum; and a second layer including activated dopant regions, the second layer overlying the at least one metal layer, wherein the second layer includes second transistors, wherein the second transistors are processed aligned to the first alignment mark with less than 100 nm alignment error, and the second transistors include mono-crystal, horizontally-oriented transistors.
摘要翻译：一种半导体器件，包括具有第一晶体管的第一单晶层和第一对准标记; 覆盖所述第一单晶层的至少一个金属层，其中所述至少一个金属层包括铜或铝; 以及包括激活的掺杂剂区域的第二层，所述第二层覆盖所述至少一个金属层，其中所述第二层包括第二晶体管，其中所述第二晶体管被处理成与所述第一对准标记对齐，具有小于100nm的对准误差，第二晶体管包括单晶，水平取向晶体管。

9. 发明授权

US07960242B2 Method for fabrication of a semiconductor device and structure 有权
标题翻译：半导体器件和结构的制造方法
公开(公告)号：US07960242B2
公开(公告)日：2011-06-14
申请号：US12847911
申请日：2010-07-30
申请人： Zvi Or-Bach , Brian Cronquist , Israel Beinglass , Jan Lodewijk de Jong , Deepak C. Sekar
发明人： Zvi Or-Bach , Brian Cronquist , Israel Beinglass , Jan Lodewijk de Jong , Deepak C. Sekar
IPC分类号： H01L21/336 , H01L21/8234 , H01L21/76
CPC分类号： G11C17/14 , H01L21/76254 , H01L21/8221 , H01L21/84 , H01L23/36 , H01L23/481 , H01L23/5252 , H01L23/544 , H01L24/45 , H01L24/48 , H01L25/0657 , H01L25/18 , H01L27/0207 , H01L27/0688 , H01L27/0694 , H01L27/092 , H01L27/105 , H01L27/10873 , H01L27/10876 , H01L27/10897 , H01L27/11 , H01L27/1104 , H01L27/1108 , H01L27/112 , H01L27/11206 , H01L27/11803 , H01L2223/5442 , H01L2223/54426 , H01L2223/54453 , H01L2224/16145 , H01L2224/32145 , H01L2224/45124 , H01L2224/45147 , H01L2224/48091 , H01L2224/73265 , H01L2225/06513 , H01L2225/06517 , H01L2225/06527 , H01L2225/06541 , H01L2225/06589 , H01L2924/00011 , H01L2924/00014 , H01L2924/01019 , H01L2924/01066 , H01L2924/01322 , H01L2924/10253 , H01L2924/12032 , H01L2924/12036 , H01L2924/1301 , H01L2924/1305 , H01L2924/13062 , H01L2924/13091 , H01L2924/14 , H01L2924/181 , H01L2924/3011 , H01L2924/3025 , H03K17/687 , H03K19/0948 , H03K19/17704 , H03K19/17756 , H03K19/17764 , H03K19/17796 , H01L2924/00 , H01L2224/80001 , H01L2224/05599 , H01L2924/00012
摘要： A method of manufacturing a semiconductor wafer, the method comprising: providing a base wafer comprising a semiconductor substrate, metal layers and first alignment marks; transferring a monocrystalline layer on top of said metal layers, wherein said monocrystalline layer comprises second alignment marks; and performing a lithography using an alignment based on a misalignment between said first alignment marks and said second alignment marks.
摘要翻译：一种制造半导体晶片的方法，所述方法包括：提供包括半导体衬底，金属层和第一对准标记的基底晶片; 在所述金属层的顶部上转移单晶层，其中所述单晶层包括第二对准标记; 以及使用基于所述第一对准标记和所述第二对准标记之间的未对准的对准来执行光刻。

10. 发明申请

US20110108888A1 SYSTEM COMPRISING A SEMICONDUCTOR DEVICE AND STRUCTURE 有权
标题翻译：包含半导体器件和结构的系统
公开(公告)号：US20110108888A1
公开(公告)日：2011-05-12
申请号：US12949617
申请日：2010-11-18
申请人： Zvi Or-Bach , Brian Cronquist , Israel Beinglass , J. L. de Jong , Deepak C. Sekar
发明人： Zvi Or-Bach , Brian Cronquist , Israel Beinglass , J. L. de Jong , Deepak C. Sekar
IPC分类号： H01L27/118
CPC分类号： H01L21/8221 , H01L21/76254 , H01L21/84 , H01L23/481 , H01L23/544 , H01L27/0207 , H01L27/0688 , H01L27/105 , H01L27/10876 , H01L27/10879 , H01L27/10894 , H01L27/10897 , H01L27/11 , H01L27/1108 , H01L27/112 , H01L27/11521 , H01L27/11551 , H01L27/11578 , H01L27/11807 , H01L27/11898 , H01L27/1203 , H01L29/66795 , H01L29/78 , H01L2223/54426 , H01L2224/16145 , H01L2224/16225 , H01L2224/32145 , H01L2224/32225 , H01L2224/45124 , H01L2224/48091 , H01L2224/48227 , H01L2224/73204 , H01L2224/73253 , H01L2224/73265 , H01L2924/00011 , H01L2924/01322 , H01L2924/10253 , H01L2924/12032 , H01L2924/1301 , H01L2924/1305 , H01L2924/13062 , H01L2924/13091 , H01L2924/15311 , H01L2924/181 , H01L2924/3011 , H01L2924/3025 , H01L2924/00 , H01L2924/00014 , H01L2224/80001 , H01L2924/00012
摘要： A semiconductor device includes a first mono-crystallized layer including first transistors, and a first metal layer forming at least a portion of connections between the first transistors; and a second layer including second transistors, the second transistors including mono-crystalline material, the second layer overlying the first metal layer, wherein the first metal layer includes aluminum or copper, and wherein the second layer is less than one micron in thickness and includes logic cells.
摘要翻译：半导体器件包括包括第一晶体管的第一单结晶层和形成第一晶体管之间的连接的至少一部分的第一金属层; 以及包括第二晶体管的第二层，所述第二晶体管包括单晶材料，所述第二层覆盖所述第一金属层，其中所述第一金属层包括铝或铜，并且其中所述第二层的厚度小于1微米，并且包括逻辑单元。

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