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1. 发明申请

US20050047224A1 Partial good integrated circuit and method of testing same 有权
标题翻译：部分良好的集成电路及其测试方法
公开(公告)号：US20050047224A1
公开(公告)日：2005-03-03
申请号：US10651874
申请日：2003-08-29
申请人： Leonard Farnsworth , Michael Felske , Pamela Gillis , Benjamin Lynch , Michael Ouellette , Thomas St.Pierre , Tad Wilder , Carl Barnhart
发明人： Leonard Farnsworth , Michael Felske , Pamela Gillis , Benjamin Lynch , Michael Ouellette , Thomas St.Pierre , Tad Wilder , Carl Barnhart
IPC分类号： G01R31/3185 , G11C7/00 , G11C29/00
CPC分类号： G01R31/318558 , G01R31/318505 , G01R31/318516 , G11C2029/1208 , G11C2029/3202
摘要： An integrated circuit, including: a multiplicity of macro-circuits, each macro-circuit having the same function; a fuse bank containing a multiplicity of fuses, the state of the fuses storing test data indicating at least which macro-circuits failed a test; and means for preventing utilization of failing macro-circuits during operation of the integrated circuit and a method generating a partial good integrated circuit, the method including: providing an integrated circuit have a multiplicity of macro-circuits arranged in one or more groups, each macro-circuit having the same function and a fuse bank containing fuses; testing each macro-circuit prior to a fuse programming operation; programming the fuses in the fuse bank in order to store data indicating at least which macro-circuits failed the testing step; and preventing utilization of each failing macro-circuit during operation of the integrated based on the data stored in the fuse bank.
摘要翻译：一种集成电路，包括：多个宏电路，每个宏电路具有相同的功能; 包含多个保险丝的保险丝库，保险丝的状态存储测试数据，至少指示哪些宏电路测试失败; 以及用于防止在集成电路运行期间利用故障宏电路的装置和产生部分良好集成电路的方法，所述方法包括：提供集成电路，其具有以一组或多组布置的多个宏电路，每个宏具有相同功能的电路和包含保险丝的保险丝库; 在保险丝编程操作之前测试每个宏电路; 对保险丝组中的熔丝进行编程，以便存储指示测试步骤中至少哪些宏电路失败的数据; 并且基于存储在熔丝库中的数据，防止在集成的操作期间利用每个故障的宏电路。

2. 发明申请

US20080010571A1 PARTIAL GOOD INTEGRATED CIRCUIT AND METHOD OF TESTING SAME 失效
公开(公告)号：US20080010571A1
公开(公告)日：2008-01-10
申请号：US11859834
申请日：2007-09-24
申请人： Leonard Farnsworth , Michael Felske , Pamela Gillis , Benjamin Lynch , Michael Ouellette , Thomas St. Pierre , Tad Wilder , Carl Barnhart
发明人： Leonard Farnsworth , Michael Felske , Pamela Gillis , Benjamin Lynch , Michael Ouellette , Thomas St. Pierre , Tad Wilder , Carl Barnhart
IPC分类号： G06F11/25
CPC分类号： G01R31/318558 , G01R31/318505 , G01R31/318516 , G11C2029/1208 , G11C2029/3202
摘要： An integrated circuit and method of testing and repairing the integrated circuit. The integrated circuit includes: a multiplicity of macro-circuits having the same function; a fuse bank, the state of the fuses storing test data indicating at least which macro-circuits failed a test; and means for preventing utilization of failing macro-circuits during operation of the integrated circuit and a method generating a partial good integrated circuit, the method including: providing an integrated circuit have a multiplicity of macro-circuits arranged in one or more groups, each macro-circuit having the same function and a fuse bank containing fuses; testing each macro-circuit prior to a fuse programming operation; programming the fuses in the fuse bank in order to store data indicating at least which macro-circuits failed the testing step; and preventing utilization of each failing macro-circuit during operation of the integrated based on the data stored in the fuse bank.

3. 发明授权

US07979764B2 Distributed test compression for integrated circuits 有权
标题翻译：集成电路的分布式测试压缩
公开(公告)号：US07979764B2
公开(公告)日：2011-07-12
申请号：US11933853
申请日：2007-11-01
申请人： Brian Foutz , Patrick Gallagher , Vivek Chickermane , Carl Barnhart
发明人： Brian Foutz , Patrick Gallagher , Vivek Chickermane , Carl Barnhart
IPC分类号： G01R31/28
CPC分类号： G06F11/267 , G01R31/318547
摘要： A method for testing integrated circuits is provided. The method provides for incorporating compression and decompression logic into each sub-component of an integrated circuit, developing test modes that target different sub-components of the integrated circuit, selecting one of the test modes, applying a test pattern to one or more sub-components of the integrated circuit targeted by the one test mode, comparing a response from application of the test pattern to a known good response, and diagnosing the response to determine which part of the one or more sub-components targeted by the one test mode failed when the response does not match the known good response.
摘要翻译：提供了一种用于测试集成电路的方法。该方法提供将压缩和解压缩逻辑并入到集成电路的每个子组件中，开发针对集成电路的不同子组件的测试模式，选择测试模式之一，将测试模式应用于一个或多个子模块，由一个测试模式所针对的集成电路的组件，将来自应用测试模式的响应与已知的良好响应进行比较，以及诊断响应以确定由一个测试模式所针对的一个或多个子组件的哪个部分失败当响应与已知的良好响应不匹配时。

4. 发明申请

US20090119559A1 DISTRIBUTED TEST COMPRESSION FOR INTEGRATED CIRCUITS 有权
标题翻译：集成电路分布式测试压缩
公开(公告)号：US20090119559A1
公开(公告)日：2009-05-07
申请号：US11933853
申请日：2007-11-01
申请人： Brian Foutz , Patrick Gallagher , Vivek Chickermane , Carl Barnhart
发明人： Brian Foutz , Patrick Gallagher , Vivek Chickermane , Carl Barnhart
IPC分类号： G01R31/28 , G06F11/25
CPC分类号： G06F11/267 , G01R31/318547
摘要： A method for testing integrated circuits is provided. The method provides for incorporating compression and decompression logic into each sub-component of an integrated circuit, developing test modes that target different sub-components of the integrated circuit, selecting one of the test modes, applying a test pattern to one or more sub-components of the integrated circuit targeted by the one test mode, comparing a response from application of the test pattern to a known good response, and diagnosing the response to determine which part of the one or more sub-components targeted by the one test mode failed when the response does not match the known good response.
摘要翻译：提供了一种用于测试集成电路的方法。该方法提供将压缩和解压缩逻辑并入到集成电路的每个子组件中，开发针对集成电路的不同子组件的测试模式，选择测试模式之一，将测试模式应用于一个或多个子模块，由一个测试模式所针对的集成电路的组件，将来自应用测试模式的响应与已知的良好响应进行比较，以及诊断响应以确定由一个测试模式所针对的一个或多个子组件的哪个部分失败当响应与已知的良好响应不匹配时。

5. 发明授权

US06611933B1 Real-time decoder for scan test patterns 失效
标题翻译：扫描测试模式的实时解码器
公开(公告)号：US06611933B1
公开(公告)日：2003-08-26
申请号：US09547827
申请日：2000-04-12
申请人： Bernd Koenemann , Carl Barnhart , Brion Keller
发明人： Bernd Koenemann , Carl Barnhart , Brion Keller
IPC分类号： G01R3128
CPC分类号： G01R31/318547
摘要： A method and apparatus for improving the efficiency of scan testing of integrated circuits is described. This efficiency is achieved by reducing the amount of required test stimulus source data and by increasing the effective bandwidth of the scan-load operation. The reduced test data volume and corresponding test time are achieved by integrating a real-time test data decoder or logic network into each integrated circuit chip. The apparatus, servicing a plurality of internal scan chains wherein the number of said internal scan chains exceeds the number of primary inputs available for loading data into the scan chains, includes: a) logic network positioned between the primary inputs and the inputs of the scan chains, the logic network expanding input data words having a width corresponding to the number of the primary inputs, and converting the input data words into expanded output data words having a width that corresponds to the number of the internal scan chains; and b) coupled to the internal scan chains, registers loaded with bit values provided by the expanded output data words while data previously loaded into the scan chains shifts forward within the scan chains by one bit position at a time; wherein a first plurality of the input data words supplied to the primary inputs produce a second plurality of expanded data words that are loaded into the internal scan chains to achieve an improved test coverage.
摘要翻译：描述了一种提高集成电路扫描测试效率的方法和装置。该效率通过减少所需的测试刺激源数据量并通过增加扫描负载操作的有效带宽来实现。通过将实时测试数据解码器或逻辑网络集成到每个集成电路芯片中来实现降低的测试数据量和相应的测试时间。该装置服务于多个内部扫描链，其中所述内部扫描链的数量超过可用于将数据加载到扫描链中的主要输入的数量，包括：a）位于主要输入和扫描的输入之间的逻辑网络所述逻辑网络扩展具有与所述主要输入的数量对应的宽度的输入数据字，以及将所述输入数据字转换成具有与所述内部扫描链的数量相对应的宽度的扩展的输出数据字; 并且b）耦合到内部扫描链，加载由扩展的输出数据字提供的位值的寄存器，而预先加载到扫描链中的数据在扫描链中每次向前移动一位位置; 其中提供给主输入的第一多个输入数据字产生加载到内部扫描链中的第二多个扩展数据字，以实现改进的测试覆盖。

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