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1. 发明申请

US20060179272A1 Data processing system, method and interconnect fabric for partial response accumulation in a data processing system 失效
标题翻译：数据处理系统，数据处理系统部分响应累积的方法和互连结构
公开(公告)号：US20060179272A1
公开(公告)日：2006-08-10
申请号：US11055297
申请日：2005-02-10
申请人： Leo Clark , James Fields , Guy Guthrie , William Starke , Jeffrey Stuecheli
发明人： Leo Clark , James Fields , Guy Guthrie , William Starke , Jeffrey Stuecheli
IPC分类号： G06F15/00
CPC分类号： G06F13/385 , G06F9/546
摘要： A data processing system includes a plurality of processing units each having a respective point-to-point communication link with each of multiple others of the plurality of processing units but fewer than all of the plurality of processing units. Each of the plurality of processing units includes interconnect logic, coupled to each point-to-point communication link of that processing unit, that broadcasts requests received from one of the multiple others of the plurality of processing units to one or more of the plurality of processing units. The interconnect logic includes a partial response data structure including a plurality of entries each associating a partial response field with a plurality of flags respectively associated with each processing unit containing a snooper from which that processing unit will receive a partial response. The interconnect logic accumulates partial responses of processing units by reference to the partial response field to obtain an accumulated partial response, and when the plurality of flags indicate that all processing units from which partial responses are expected have returned a partial response, outputs the accumulated partial response.
摘要翻译：数据处理系统包括多个处理单元，每个处理单元各自具有与多个处理单元中的多个其他处理单元中的每一个相对的点对点通信链路，但是比所有多个处理单元少。多个处理单元中的每一个包括互连逻辑，其耦合到该处理单元的每个点对点通信链路，其将从多个处理单元中的多个其中一个的接收的请求广播到多个处理单元中的一个或多个处理单位。互连逻辑包括部分响应数据结构，其包括多个条目，每个条目将部分响应字段与分别与包含窥探者的每个处理单元相关联的多个标志相关联，该处理单元将从该处理单元接收部分响应。互连逻辑通过参考部分响应字段积累处理单元的部分响应以获得累积的部分响应，并且当多个标志指示预期部分响应的所有处理单元已经返回部分响应时，输出累积的部分响应响应。

2. 发明申请

US20060179254A1 Data processing system, method and interconnect fabric supporting destination data tagging 有权
标题翻译：数据处理系统，方法和互连结构支持目标数据标记
公开(公告)号：US20060179254A1
公开(公告)日：2006-08-10
申请号：US11055405
申请日：2005-02-10
申请人： Leo Clark , James Fields , Guy Guthrie , William Starke , Jeffrey Stuecheli
发明人： Leo Clark , James Fields , Guy Guthrie , William Starke , Jeffrey Stuecheli
IPC分类号： G06F13/28
CPC分类号： G06F15/16
摘要： A data processing system includes a plurality of communication links and a plurality of processing units including a local master processing unit. The local master processing unit includes interconnect logic that couples the processing unit to one or more of the plurality of communication links and an originating master coupled to the interconnect logic. The originating master originates an operation by issuing a write-type request on at least one of the one or more communication links, receives from a snooper in the data processing system a destination tag identifying a route to the snooper, and, responsive to receipt of the combined response and the destination tag, initiates a data transfer including a data payload and a data tag identifying the route provided within the destination tag.
摘要翻译：数据处理系统包括多个通信链路和包括本地主处理单元的多个处理单元。本地主处理单元包括将处理单元耦合到多个通信链路中的一个或多个以及耦合到互连逻辑的始发主机的互连逻辑。始发主机通过在一个或多个通信链路中的至少一个发出写入请求来发起操作，从数据处理系统中的窥探者接收标识到窥探者的路由的目的地标签，并且响应于接收到组合响应和目的地标签，发起包括数据有效载荷和标识目的地标签内提供的路由的数据标签的数据传输。

3. 发明申请

US20080028155A1 DATA PROCESSING SYSTEM AND METHOD FOR EFFICIENT COHERENCY COMMUNICATION UTILIZING COHERENCY DOMAIN INDICATORS 有权
标题翻译：数据处理系统和方法，用于有效的通信使用相关域指标
公开(公告)号：US20080028155A1
公开(公告)日：2008-01-31
申请号：US11835259
申请日：2007-08-07
申请人： JAMES FIELDS , Guy Guthrie , William Starke , Jeffrey Stuecheli
发明人： JAMES FIELDS , Guy Guthrie , William Starke , Jeffrey Stuecheli
IPC分类号： G06F12/00
CPC分类号： G06F12/0831 , G06F12/0813 , G06F12/0826
摘要： In a cache coherent data processing system including at least first and second coherency domains, a memory block is stored in a system memory in association with a domain indicator indicating whether or not the memory block is cached, if at all, only within the first coherency domain. A master in the first coherency domain determines whether or not a scope of broadcast transmission of an operation should extend beyond the first coherency domain by reference to the domain indicator stored in the cache and then performs a broadcast of the operation within the cache coherent data processing system in accordance with the determination.
摘要翻译：在包括至少第一和第二相干域的缓存相干数据处理系统中，存储器块与指示是否缓存存储器块的域指示符相关联地存储在系统存储器中，如果有的话，只有在第一一致性内域。第一相干域中的主设备通过参考存储在高速缓存中的域指示符来确定操作的广播传输的范围是否应超出第一相关域，然后在高速缓存相干数据处理中执行操作的广播系统按照确定。

4. 发明申请

US20070073919A1 Data processing system and method that permit pipelining of I/O write operations and multiple operation scopes 失效
标题翻译：允许I / O写入操作和多个操作范围的流水线的数据处理系统和方法
公开(公告)号：US20070073919A1
公开(公告)日：2007-03-29
申请号：US11226967
申请日：2005-09-15
申请人： George Daly , James Fields , Guy Guthrie , William Starke , Jeffrey Stuecheli
发明人： George Daly , James Fields , Guy Guthrie , William Starke , Jeffrey Stuecheli
IPC分类号： G06F13/28
CPC分类号： G06F12/0831 , G06F12/0811
摘要： A data processing system includes at least a first processing node having an input/output (I/O) controller and a second processing including a memory controller for a memory. The memory controller receives, in order, pipelined first and second DMA write operations from the I/O controller, where the first and second DMA write operations target first and second addresses, respectively. In response to the second DMA write operation, the memory controller establishes a state of a domain indicator associated with the second address to indicate an operation scope including the first processing node. In response to the memory controller receiving a data access request specifying the second address and having a scope excluding the first processing node, the memory controller forces the data access request to be reissued with a scope including the first processing node based upon the state of the domain indicator associated with the second address.
摘要翻译：数据处理系统至少包括具有输入/输出（I / O）控制器的第一处理节点和包括用于存储器的存储器控制器的第二处理。存储器控制器按顺序从I / O控制器接收流水线的第一和第二DMA写入操作，其中第一和第二DMA写操作分别针对第一和第二地址。响应于第二DMA写入操作，存储器控制器建立与第二地址相关联的域指示符的状态，以指示包括第一处理节点的操作范围。响应于所述存储器控制器接收到指定所述第二地址并且具有排除所述第一处理节点的范围的数据访问请求，所述存储器控制器基于所述第一处理节点的状态强迫所述数据访问请求被重新发布，所述范围包括所述第一处理节点与第二个地址关联的域指示符。

5. 发明申请

US20060179249A1 Data processing system and method for predictively selecting a scope of broadcast of an operation utilizing a location of a memory 有权
标题翻译：数据处理系统和方法，用于使用存储器的位置预测性地选择操作的广播范围
公开(公告)号：US20060179249A1
公开(公告)日：2006-08-10
申请号：US11055697
申请日：2005-02-10
申请人： James Fields , Benjiman Goodman , Guy Guthrie , William Starke , Jeffrey Stuecheli , Phillip Williams
发明人： James Fields , Benjiman Goodman , Guy Guthrie , William Starke , Jeffrey Stuecheli , Phillip Williams
IPC分类号： G06F13/28
CPC分类号： G06F12/0831 , G06F12/0813
摘要： A cache coherent data processing system includes a memory and at least first and second coherency domains that each include a respective one of first and second cache memories. A master in the first coherency domain selects a scope of an initial broadcast of an operation targeting a request address allocated to the memory from among a first scope including only the first coherency domain and a second scope including both the first and second coherency domains. The master selects the scope based, at least in part, upon whether the memory belongs to the first coherency domain and performs an initial broadcast of the operation within the cache coherent data processing system utilizing the selected scope.
摘要翻译：高速缓存一致数据处理系统包括存储器和至少第一和第二一致性域，每个域包括第一和第二高速缓存存储器中的相应一个。第一相干域中的主机从仅包括第一相关域的第一范围和包括第一和第二相干域的第二范围中选择针对分配给存储器的请求地址的操作的初始广播的范围。主设备至少部分地基于所述存储器是否属于第一相关域并且使用所选择的范围来执行在高速缓存相干数据处理系统内的操作的初始广播来选择所述范围。

6. 发明申请

US20070168618A1 Data processing system, cache system and method for precisely forming an invalid coherency state indicating a broadcast scope 失效
标题翻译：数据处理系统，缓存系统和精确形成指示广播范围的无效一致性状态的方法
公开(公告)号：US20070168618A1
公开(公告)日：2007-07-19
申请号：US11333615
申请日：2006-01-17
申请人： Leo Clark , Guy Guthrie , William Starke , Jeffrey Stuecheli , Derek Williams
发明人： Leo Clark , Guy Guthrie , William Starke , Jeffrey Stuecheli , Derek Williams
IPC分类号： G06F13/28
CPC分类号： G06F12/0831
摘要： A cache coherent data processing system includes at least first and second coherency domains. In a first cache memory within the first coherency domain of the data processing system, a memory block is held in a storage location associated with an address tag and a coherency state field. A determination is made if a home system memory assigned an address associated with the memory block is within the first coherency domain. If not, the coherency state field is set to a coherency state that indicates that the address tag is valid, that the storage location does not contain valid data, the first coherency domain does not contain the home system memory, and that, following formation of the coherency state, the memory block is cached outside of the first coherency domain.
摘要翻译：缓存相干数据处理系统至少包括第一和第二相干域。在数据处理系统的第一相关域内的第一高速缓存存储器中，存储块被保存在与地址标签和一致性状态字段相关联的存储位置中。如果分配了与存储器块相关联的地址的归属系统存储器在第一相干域内，则确定。如果不是，则将一致性状态字段设置为指示地址标签有效的一致性状态，即存储位置不包含有效数据，第一相干域不包含家庭系统存储器，并且在形成一致性状态下，内存块被缓存在第一个相干域之外。

7. 发明申请

US20080052471A1 DATA PROCESSING SYSTEM AND METHOD FOR EFFICIENT COMMUNICATION UTILIZING AN IG COHERENCY STATE 失效
标题翻译：数据处理系统和使用IG语音状态的高效通信的方法
公开(公告)号：US20080052471A1
公开(公告)日：2008-02-28
申请号：US11836965
申请日：2007-08-10
申请人： JAMES FIELDS, JR. , Guy Guthrie , William Starke , Jeffrey Stuecheli
发明人： JAMES FIELDS, JR. , Guy Guthrie , William Starke , Jeffrey Stuecheli
IPC分类号： G06F12/08
CPC分类号： G06F12/0831 , G06F12/0813
摘要： A cache coherent data processing system includes at least first and second coherency domains each including at least one processing unit and a cache memory. The cache memory includes a cache controller, a data array including a data storage location for caching a memory block, and a cache directory. The cache directory includes a tag field for storing an address tag in association with the memory block and a coherency state field associated with the tag field and the data storage location. The coherency state field has a plurality of possible states including a state that indicates that the address tag is valid, that the storage location does not contain valid data, and that the memory block is possibly cached outside of the first coherency domain.
摘要翻译：高速缓存一致数据处理系统至少包括第一和第二相关域，每个域包括至少一个处理单元和高速缓冲存储器。高速缓存存储器包括高速缓存控制器，包括用于高速缓存存储器块的数据存储位置的数据阵列和高速缓存目录。缓存目录包括用于存储与存储器块相关联的地址标签的标签字段和与标签字段和数据存储位置相关联的一致性状态字段。一致性状态字段具有多个可能的状态，包括指示地址标签有效的状态，存储位置不包含有效数据，并且存储器块可能被高速缓存在第一相干域之外。

8. 发明申请

US20060179247A1 Data processing system and method for efficient communication utilizing an Ig coherency state 失效
公开(公告)号：US20060179247A1
公开(公告)日：2006-08-10
申请号：US11055524
申请日：2005-02-10
申请人： James Fields , Guy Guthrie , William Starke , Jeffrey Stuecheli
发明人： James Fields , Guy Guthrie , William Starke , Jeffrey Stuecheli
IPC分类号： G06F13/28
CPC分类号： G06F12/0831 , G06F12/0813
摘要： A cache coherent data processing system includes at least first and second coherency domains each including at least one processing unit and a cache memory. The cache memory includes a cache controller, a data array including a data storage location for caching a memory block, and a cache directory. The cache directory includes a tag field for storing an address tag in association with the memory block and a coherency state field associated with the tag field and the data storage location. The coherency state field has a plurality of possible states including a state that indicates that the address tag is valid, that the storage location does not contain valid data, and that the memory block is possibly cached outside of the first coherency domain.

9. 发明申请

US20060176906A1 Data processing system, method and interconnect fabric for selective link information allocation in a data processing system 失效
公开(公告)号：US20060176906A1
公开(公告)日：2006-08-10
申请号：US11055366
申请日：2005-02-10
申请人： James Fields , Guy Guthrie , William Starke , Jeffrey Stuecheli
发明人： James Fields , Guy Guthrie , William Starke , Jeffrey Stuecheli
IPC分类号： H04J3/22 , H04J3/16 , H04L12/26 , H04J3/14
CPC分类号： G06F15/177 , G06F12/0831 , G06F12/0897
摘要： A data processing system includes a plurality of processing units coupled for communication by a communication link and a configuration register. The configuration register has a plurality of different settings each corresponding to a respective one of a plurality of different link information allocations. Information is communicated over the communication link in accordance with a particular link information allocation among the plurality of link information allocations determined by a respective setting of the configuration register.

10. 发明申请

US20060179246A1 Data processing system and method for efficient coherency communication utilizing coherency domain indicators 有权
标题翻译：数据处理系统和方法，利用相干域指标进行有效的一致性通信
公开(公告)号：US20060179246A1
公开(公告)日：2006-08-10
申请号：US11055483
申请日：2005-02-10
申请人： James Fields , Guy Guthrie , William Starke , Jeffrey Stuecheli
发明人： James Fields , Guy Guthrie , William Starke , Jeffrey Stuecheli
IPC分类号： G06F13/28
CPC分类号： G06F12/0831 , G06F12/0813 , G06F12/0826
摘要： In a cache coherent data processing system including at least first and second coherency domains, a memory block is stored in a system memory in association with a domain indicator indicating whether or not the memory block is cached, if at all, only within the first coherency domain. A master in the first coherency domain determines whether or not a scope of broadcast transmission of an operation should extend beyond the first coherency domain by reference to the domain indicator stored in the cache and then performs a broadcast of the operation within the cache coherent data processing system in accordance with the determination.
摘要翻译：在包括至少第一和第二相干域的缓存相干数据处理系统中，存储器块与指示是否缓存存储器块的域指示符相关联地存储在系统存储器中，如果有的话，只有在第一一致性内域。第一相干域中的主设备通过参考存储在高速缓存中的域指示符来确定操作的广播传输的范围是否应超出第一相关域，然后在高速缓存相干数据处理中执行操作的广播系统按照确定。

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