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    • 1. 发明申请
    • System and Method for Priority-Based Prefetch Requests Scheduling and Throttling
    • 基于优先级的预取请求调度和调节的系统和方法
    • US20090199190A1
    • 2009-08-06
    • US12024389
    • 2008-02-01
    • Lei ChenLixin Zhang
    • Lei ChenLixin Zhang
    • G06F9/46
    • G06F12/0862G06F9/3455G06F9/383G06F2212/1016
    • A method, processor, and data processing system for implementing a framework for priority-based scheduling and throttling of prefetching operations. A prefetch engine (PE) assigns a priority to a first prefetch stream, indicating a relative priority for scheduling prefetch operations of the first prefetch stream. The PE monitors activity within the data processing system and dynamically updates the priority of the first prefetch stream based on the activity (or lack thereof). Low priority streams may be discarded. The PE also schedules prefetching in a priority-based scheduling sequence that corresponds to the priority currently assigned to the scheduled active streams. When there are no prefetches within a prefetch queue, the PE triggers the active streams to provide prefetches for issuing. The PE determines when to throttle prefetching, based on the current usage level of resources relevant to completing the prefetch.
    • 一种用于实现基于优先级调度和限制预取操作的框架的方法,处理器和数据处理系统。 预取引擎(PE)将优先级分配给第一预取流,指示用于调度第一预取流的预取操作的相对优先级。 PE监视数据处理系统内的活动,并基于活动(或缺乏)动态地更新第一预取流的优先级。 低优先级流可能被丢弃。 PE还在基于优先级的调度序列中调度预取,该调度序列对应于当前分配给调度的活动流的优先级。 当预取队列中没有预取时,PE触发活动流以提供预取。 根据与完成预取相关的资源的当前使用水平,PE确定何时限制预取。
    • 2. 发明授权
    • Priority-based prefetch requests scheduling and throttling
    • 基于优先级的预取请求调度和调节
    • US08255631B2
    • 2012-08-28
    • US12024389
    • 2008-02-01
    • Lei ChenLixin Zhang
    • Lei ChenLixin Zhang
    • G06F12/00G06F9/00
    • G06F12/0862G06F9/3455G06F9/383G06F2212/1016
    • A method, processor, and data processing system for implementing a framework for priority-based scheduling and throttling of prefetching operations. A prefetch engine (PE) assigns a priority to a first prefetch stream, indicating a relative priority for scheduling prefetch operations of the first prefetch stream. The PE monitors activity within the data processing system and dynamically updates the priority of the first prefetch stream based on the activity (or lack thereof). Low priority streams may be discarded. The PE also schedules prefetching in a priority-based scheduling sequence that corresponds to the priority currently assigned to the scheduled active streams. When there are no prefetches within a prefetch queue, the PE triggers the active streams to provide prefetches for issuing. The PE determines when to throttle prefetching, based on the current usage level of resources relevant to completing the prefetch.
    • 一种用于实现基于优先级调度和限制预取操作的框架的方法,处理器和数据处理系统。 预取引擎(PE)将优先级分配给第一预取流,指示用于调度第一预取流的预取操作的相对优先级。 PE监视数据处理系统内的活动,并基于活动(或缺乏)动态地更新第一预取流的优先级。 低优先级流可能被丢弃。 PE还在基于优先级的调度序列中调度预取,该调度序列对应于当前分配给调度的活动流的优先级。 当预取队列中没有预取时,PE触发活动流以提供预取。 根据与完成预取相关的资源的当前使用水平,PE确定何时限制预取。
    • 3. 发明申请
    • Branch Target Extension for an Instruction Cache
    • 指令缓存的分支目标扩展
    • US20080126771A1
    • 2008-05-29
    • US11459683
    • 2006-07-25
    • Lei ChenZhigang HuLixin Zhang
    • Lei ChenZhigang HuLixin Zhang
    • G06F9/38
    • G06F9/3844G06F9/3806G06F9/3814
    • An instruction cache (I-Cache) for a processor is configured to include a Branch Target Extension associated with each Instruction Sector. When an Instruction Sector is fetched, the Branch Target Extension is simultaneously fetched. If the Instruction Sector has a branch instruction that is predicted taken, then the branch target address in the branch extension is used to access the next Instruction Sector. In other embodiments, each Instruction Sector has a plurality of Branch Target Extensions each corresponding to a potential branch instruction in an Instruction Sector. In this case, the Branch Target Extensions are partitioned into an instruction index field for locating branch instruction in the Instruction Sector, a local predictor field for predicted taken status and a target address field for the branch target address. The least significant bits of the instruction fetch address are compared to the instruction indexes to determine a particular Branch Target Extension to use.
    • 用于处理器的指令高速缓存(I-Cache)被配置为包括与每个指令扇区相关联的分支目标扩展。 当获取指令扇区时,同时提取分支目标扩展。 如果指令扇区具有预测的分支指令,则分支扩展中的分支目标地址用于访问下一个指令扇区。 在其他实施例中,每个指令扇区具有多个分支目标扩展,每个分支目标扩展对应于指令扇区中的潜在分支指令。 在这种情况下,分支目标扩展被划分为用于定位指令扇区中的分支指令的指令索引字段,用于预测采用状态的本地预测器字段和用于分支目标地址的目标地址字段。 将指令提取地址的最低有效位与指令索引进行比较,以确定要使用的特定分支目标扩展。
    • 4. 发明授权
    • Indexed table circuit having reduced aliasing
    • 索引表电路具有减少的混叠
    • US08086831B2
    • 2011-12-27
    • US12024241
    • 2008-02-01
    • Lei ChenLixin Zhang
    • Lei ChenLixin Zhang
    • G06F9/35G06F9/355
    • G06F9/3848
    • In at least one embodiment, an indexed table circuit includes a plurality of banks for storing data to be accessed and a split index array. The indexed table circuit is organized in a plurality of entries each corresponding to a respective one of a plurality of different entry indices, where each entry includes a storage location in the plurality of banks and the split index array. The indexed table circuit further includes selection logic that, responsive to read access of an entry among the plurality of entries utilizing an entry index of a bit string, utilizes a split index read from the split index array to select a set of one or more bits of a tag of the bit string, utilizes the selected set of one or more bits to select data read from one of the plurality of banks, and outputs the selected data.
    • 在至少一个实施例中,索引表电路包括用于存储要访问的数据的多个存储体和分离索引阵列。 索引表电路被组织成多个条目,每个条目对应于多个不同入口索引中的相应一个,其中每个条目包括多个存储体中的存储位置和拆分索引阵列。 索引表电路还包括选择逻辑,其响应于使用位串的条目索引的多个条目中的条目的读取访问,利用从拆分索引数组读取的拆分索引来选择一个或多个位的集合 使用所选择的一个或多个位的集合来选择从多个存储体之一读取的数据,并输出所选择的数据。