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1. 发明申请

US20130191852A1 Multithreaded Computing 审中-公开
标题翻译：多线程计算
公开(公告)号：US20130191852A1
公开(公告)日：2013-07-25
申请号：US13606741
申请日：2012-09-07
申请人： Lee W. Howes , Benedict R. Gaster , Michael Clair Houston , Michael Mantor
发明人： Lee W. Howes , Benedict R. Gaster , Michael Clair Houston , Michael Mantor
IPC分类号： G06F9/46
CPC分类号： G06F9/542 , G06F9/4843
摘要： A system, method, and computer program product are provided for improving resource utilization of multithreaded applications. Rather than requiring threads to block while waiting for data from a channel or requiring context switching to minimize blocking, the techniques disclosed herein provide an event-driven approach to launch kernels only when needed to perform operations on channel data, and then terminate in order to free resources. These operations are handled efficiently in hardware, but are flexible enough to be implemented in all manner of programming models.
摘要翻译：提供了一种系统，方法和计算机程序产品，用于提高多线程应用程序的资源利用率。而不是要求线程在等待来自信道的数据或需要上下文切换以最小化阻塞的情况下阻塞，所以本文所公开的技术提供了仅当需要对信道数据执行操作时启动内核的事件驱动方法，然后终止以便免费资源。这些操作在硬件中有效地处理，但是具有足够的灵活性，可以在各种编程模型中实现。

2. 发明授权

US10235220B2 Multithreaded computing 有权
公开(公告)号：US10235220B2
公开(公告)日：2019-03-19
申请号：US13606741
申请日：2012-09-07
申请人： Lee W. Howes , Benedict R. Gaster , Michael Clair Houston , Michael Mantor
发明人： Lee W. Howes , Benedict R. Gaster , Michael Clair Houston , Michael Mantor
IPC分类号： G06F3/00 , G06F9/44 , G06F9/46 , G06F13/00 , G06F9/54 , G06F9/48
摘要： A system, method, and computer program product are provided for improving resource utilization of multithreaded applications. Rather than requiring threads to block while waiting for data from a channel or requiring context switching to minimize blocking, the techniques disclosed herein provide an event-driven approach to launch kernels only when needed to perform operations on channel data, and then terminate in order to free resources. These operations are handled efficiently in hardware, but are flexible enough to be implemented in all manner of programming models.

3. 发明授权

US08607247B2 Method and system for workitem synchronization 有权
标题翻译：工作同步的方法和系统
公开(公告)号：US08607247B2
公开(公告)日：2013-12-10
申请号：US13288833
申请日：2011-11-03
申请人： Lee W. Howes , Benedict R. Gaster , Michael C. Houston , Michael Mantor , Mark Leather , Norman Rubin , Brian D. Emberling
发明人： Lee W. Howes , Benedict R. Gaster , Michael C. Houston , Michael Mantor , Mark Leather , Norman Rubin , Brian D. Emberling
IPC分类号： G06F9/46 , G06F1/04 , G06F1/12 , G06F7/00
CPC分类号： G06F9/522 , G06F9/30087 , G06F9/524
摘要： Method, system, and computer program product embodiments for synchronizing workitems on one or more processors are disclosed. The embodiments include executing a barrier skip instruction by a first workitem from the group, and responsive to the executed barrier skip instruction, reconfiguring a barrier to synchronize other workitems from the group in a plurality of points in a sequence without requiring the first workitem to reach the barrier in any of the plurality of points.
摘要翻译：公开了用于在一个或多个处理器上同步工作项的方法，系统和计算机程序产品实施例。这些实施例包括通过来自组的第一工作项执行障碍跳过指令，并且响应于所执行的屏障跳过指令，重新配置屏障以在序列中的多个点中从组中的其他工作项同步，而不需要第一工作项到达在多个点中的任一个中的屏障。

4. 发明申请

US20130117750A1 Method and System for Workitem Synchronization 有权
标题翻译：工作同步方法和系统
公开(公告)号：US20130117750A1
公开(公告)日：2013-05-09
申请号：US13288833
申请日：2011-11-03
申请人： Lee W. HOWES , Benedict R. Gaster , Michael C. Houston , Michael Mantor , Mark Leather , Norman Rubin , Brian D. Emberling
发明人： Lee W. HOWES , Benedict R. Gaster , Michael C. Houston , Michael Mantor , Mark Leather , Norman Rubin , Brian D. Emberling
IPC分类号： G06F9/46
CPC分类号： G06F9/522 , G06F9/30087 , G06F9/524
摘要： Method, system, and computer program product embodiments for synchronizing workitems on one or more processors are disclosed. The embodiments include executing a barrier skip instruction by a first workitem from the group, and responsive to the executed barrier skip instruction, reconfiguring a barrier to synchronize other workitems from the group in a plurality of points in a sequence without requiring the first workitem to reach the barrier in any of the plurality of points.
摘要翻译：公开了用于在一个或多个处理器上同步工作项的方法，系统和计算机程序产品实施例。这些实施例包括通过来自组的第一工作项执行障碍跳过指令，并且响应于所执行的屏障跳过指令，重新配置屏障以在序列中的多个点中从组中的其他工作项同步，而不需要第一工作项到达在多个点中的任一个中的屏障。

5. 发明授权

US09529632B2 Interlocked increment memory allocation and access 有权
标题翻译：联锁增量内存分配和访问
公开(公告)号：US09529632B2
公开(公告)日：2016-12-27
申请号：US12553652
申请日：2009-09-03
申请人： Michael Mantor , John McCardle , Marcos Zini , Brian Emberling
发明人： Michael Mantor , John McCardle , Marcos Zini , Brian Emberling
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28 , G06F9/50
CPC分类号： G06F9/5016
摘要： A method of allocating a memory to a plurality of concurrent threads is presented. The method includes dynamically determining writer threads each having at least one pending write to the memory; and dynamically allocating respective contiguous blocks in the memory for each of the writer threads. Another method of allocating a memory to a plurality of concurrent threads includes launching the plurality of threads as a plurality of wavefronts, dynamically determining a group of wavefronts each having at least one thread requiring a write to the memory, and dynamically allocating respective contiguous blocks in the memory for each wavefront from the group of wavefronts. A corresponding method of assigning a memory to a plurality of reader threads includes determining a first number corresponding to a number of writer threads having a block allocated in said memory, launching a first number of reader threads, entering a first wavefront of said reader threads from said group of wavefronts to an atomic operation, and assigning a first block in the memory to the first wavefront during the corresponding atomic operation, where the first block is contiguous to a previously allocated block dynamically allocated to another wavefront from said group of wavefronts. Corresponding system embodiments and computer program product embodiments are also presented.
摘要翻译：提出了一种向多个并发线程分配存储器的方法。该方法包括动态地确定写入器线程，每个写入器线程具有至少一个待写入到存储器的并为每个写入器线程动态地分配存储器中的相应连续块。向多个并发线程分配存储器的另一种方法包括：将多个线程作为多个波前发射，动态地确定每组具有至少一个需要对存储器进行写入的线程的波前组，以及动态分配相应的连续块从波浪组的每个波前的记忆。将存储器分配给多个读取器线程的相应方法包括确定与具有在所述存储器中分配的块的写入器线程数相对应的第一数字，启动第一数量的读取器线程，从所述读取器线程的第一波前输入所述波束组合到原子操作，并且在相应的原子操作期间将第一块在存储器中分配给第一波阵面，其中第一块与先前分配的块相邻，所述块先前从所述波阵组中分配给另一波阵面。还提出了相应的系统实施例和计算机程序产品实施例。

6. 发明授权

US09122522B2 Software mechanisms for managing task scheduling on an accelerated processing device (APD) 有权
标题翻译：用于管理加速处理设备（APD）上的任务调度的软件机制
公开(公告)号：US09122522B2
公开(公告)日：2015-09-01
申请号：US13325755
申请日：2011-12-14
申请人： Robert Scott Hartog , Ralph Clay Taylor , Michael Mantor , Thomas Roy Woller , Kevin McGrath , Sebastien Nussbaum , Nuwan S. Jayasena , Rex McCrary , Philip J. Rogers , Mark Leather
发明人： Robert Scott Hartog , Ralph Clay Taylor , Michael Mantor , Thomas Roy Woller , Kevin McGrath , Sebastien Nussbaum , Nuwan S. Jayasena , Rex McCrary , Philip J. Rogers , Mark Leather
IPC分类号： G06F9/46 , G06F9/48 , G06F9/50
CPC分类号： G06F9/4881 , G06F9/5027 , G06F2209/5013 , G06F2209/508 , G06F2209/509
摘要： Embodiments describe herein provide a method of for managing task scheduling on a accelerated processing device. The method includes executing a first task within the accelerated processing device (APD), monitoring for an interruption of the execution of the first task, and switching to a second task when an interruption is detected.
摘要翻译：本文描述的实施例提供了一种用于在加速处理设备上管理任务调度的方法。该方法包括在加速处理设备（APD）内执行第一任务，监视第一任务的执行中断，以及当检测到中断时切换到第二任务。

7. 发明申请

US20130160019A1 Method for Resuming an APD Wavefront in Which a Subset of Elements Have Faulted 有权
标题翻译：恢复其中元素子集发生故障的APD波前的方法
公开(公告)号：US20130160019A1
公开(公告)日：2013-06-20
申请号：US13325298
申请日：2011-12-14
申请人： Robert Scott HARTOG , Ralph Clay Taylor , Michael Mantor , Thomas R, Woller , Kevin McGrath , Sebastien Nussbaum , Nuwan Jayasena , Rex McCrary , Philip J. Rogers , Mark Leather
发明人： Robert Scott HARTOG , Ralph Clay Taylor , Michael Mantor , Thomas R, Woller , Kevin McGrath , Sebastien Nussbaum , Nuwan Jayasena , Rex McCrary , Philip J. Rogers , Mark Leather
IPC分类号： G06F9/50
CPC分类号： G06F9/4843
摘要： A method resumes an accelerated processing device (APD) wavefront in which a subset of elements have faulted. A restore command for a job including a wavefront is received. A list of context states for the wavefront is read from a memory associated with a APD. An empty shell wavefront is created for restoring the list of context states. A portion of not acknowledged data is masked over a portion of acknowledged data within the restored wavefronts.
摘要翻译：一种方法恢复加速处理设备（APD）波前，其中元素的子集已经发生故障。接收到包含波前的作业的恢复命令。从与APD相关联的存储器中读取波阵面的上下文状态列表。创建一个空壳波阵面用于恢复上下文状态列表。一部分未确认的数据被掩蔽在恢复的波前的一部分确认数据上。

8. 发明申请

US20130145202A1 Handling Virtual-to-Physical Address Translation Failures 审中-公开
标题翻译：处理虚拟到物理地址转换失败
公开(公告)号：US20130145202A1
公开(公告)日：2013-06-06
申请号：US13311822
申请日：2011-12-06
申请人： Robert Scott Hartog , Ralph Clay Taylor , Michael Mantor , Thomas R. Woller , Sebastien Nussbaum , Rex McCrary , Philip J. Rogers , Mark Leather
发明人： Robert Scott Hartog , Ralph Clay Taylor , Michael Mantor , Thomas R. Woller , Sebastien Nussbaum , Rex McCrary , Philip J. Rogers , Mark Leather
IPC分类号： G06F11/07
CPC分类号： G06F12/1027 , G06F12/1081
摘要： A method tolerates virtual to physical address translation failures. A translation request is sent from a graphics processing device to a translation mechanism. The translation request is associated with a first wavefront. A fault notification is received within an accelerated processing device (APD) from the translation mechanism that a request cannot be acknowledged. The first wavefront is, stored within a shader core of the APD if the fault notification is received. The first wavefront is replaced with a second wavefront if the fault notification is received, the second wavefront being ready to be executed.
摘要翻译：一种方法允许虚拟到物理地址转换失败。翻译请求从图形处理装置发送到翻译机构。翻译请求与第一个波前相关联。在来自转换机制的加速处理设备（APD）中接收到不能确认请求的故障通知。如果接收到故障通知，第一个波阵面存储在APD的着色器核心内。如果接收到故障通知，则第一个波前被替换为第二个波阵面，第二个波阵面准备好执行。

9. 发明授权

US08281183B2 Apparatus with redundant circuitry and method therefor 有权
标题翻译：具有冗余电路的装置及其方法
公开(公告)号：US08281183B2
公开(公告)日：2012-10-02
申请号：US12509803
申请日：2009-07-27
申请人： Michael Mantor , Ralph Clayton Taylor , Robert Scott Hartog
发明人： Michael Mantor , Ralph Clayton Taylor , Robert Scott Hartog
IPC分类号： G06F11/00
CPC分类号： G06F11/2028 , G06F11/2038 , G06F11/2048
摘要： An apparatus with circuit redundancy includes a set of parallel arithmetic logic units (ALUs), a redundant parallel ALU, input data shifting logic that is coupled to the set of parallel ALUs and that is operatively coupled to the redundant parallel ALU. The input data shifting logic shifts input data for a defective ALU, in a first direction, to a neighboring ALU in the set. When the neighboring ALU is the last or end ALU in the set, the shifting logic continues to shift the input data for the end ALU that is not defective, to the redundant parallel ALU. The redundant parallel ALU then operates for the defective ALU. Output data shifting logic is coupled to an output of the parallel redundant ALU and all other ALU outputs to shift the output data in a second and opposite direction than the input shifting logic, to realign output of data for continued processing, including for storage or for further processing by other circuitry.
摘要翻译：具有电路冗余的装置包括一组并行算术逻辑单元（ALU），冗余并行ALU，输入数据移位逻辑，其耦合到该组并行ALU并且可操作地耦合到冗余并行ALU。输入数据移位逻辑将有缺陷的ALU的输入数据沿第一方向移动到该组中的相邻ALU。当相邻的ALU是组中的最后一个或结束ALU时，移位逻辑继续将没有故障的结束ALU的输入数据移动到冗余并行ALU。冗余的并行ALU然后对有缺陷的ALU进行操作。输出数据移位逻辑耦合到并行冗余ALU和所有其他ALU输出的输出，以使输出数据在与输入移位逻辑相反的方向上相反的方向上移位，以重新输出用于继续处理的数据输出，包括用于存储或用于由其他电路进一步处理。

10. 发明申请

US20060053189A1 GRAPHICS PROCESSING LOGIC WITH VARIABLE ARITHMETIC LOGIC UNIT CONTROL AND METHOD THEREFOR 有权
标题翻译：具有可变算术逻辑单元控制的图形处理逻辑及其方法
公开(公告)号：US20060053189A1
公开(公告)日：2006-03-09
申请号：US11161674
申请日：2005-08-11
申请人： Michael Mantor
发明人： Michael Mantor
IPC分类号： G06F7/38
CPC分类号： G06T15/005 , G06F11/2028 , G06F11/2038 , G06F11/2048
摘要： Briefly, graphics data processing logic includes a plurality of parallel arithmetic logic units (ALUs), such as floating point processors or any other suitable logic, that operate as a vector processor on at least one of pixel data and vertex data (or both) and a programmable storage element that contains data representing which of the plurality of arithmetic logic units are not to receive data for processing. The graphics data processing logic also includes parallel ALU data packing logic that is operatively coupled to the plurality of arithmetic logic processing units and to the programmable storage element to pack data only for the plurality of arithmetic logic units identified by the data in the programmable storage element as being enabled.
摘要翻译：简而言之，图形数据处理逻辑包括多个并行算术逻辑单元（ALU），诸如浮点处理器或任何其它合适的逻辑，其在像素数据和顶点数据（或两者）中的至少一个上作为向量处理器，以及可编程存储元件，其包含表示多个算术逻辑单元中的哪一个不接收用于处理的数据的数据。图形数据处理逻辑还包括并行ALU数据打包逻辑，其可操作地耦合到多个算术逻辑处理单元和可编程存储元件，以仅对由可编程存储元件中的数据标识的多个算术逻辑单元打包数据被启用。

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