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1. 发明申请

US20070106878A1 High-performance, superscalar-based computer system with out-of-order instruction execution 失效
标题翻译：高性能，基于超标量的计算机系统，执行无序指令
公开(公告)号：US20070106878A1
公开(公告)日：2007-05-10
申请号：US11642599
申请日：2006-12-21
申请人： Le Nguyen , Derek Lentz , Yoshiyuki Miyayama , Sanjiv Garg , Yasuaki Hagiwara , Johannes Wang , Te-Li Lau , Sze-Shun Wang , Quang Trang
发明人： Le Nguyen , Derek Lentz , Yoshiyuki Miyayama , Sanjiv Garg , Yasuaki Hagiwara , Johannes Wang , Te-Li Lau , Sze-Shun Wang , Quang Trang
IPC分类号： G06F9/30
CPC分类号： G06F9/3822 , G06F9/30061 , G06F9/30072 , G06F9/30112 , G06F9/30116 , G06F9/30123 , G06F9/3013 , G06F9/30134 , G06F9/30167 , G06F9/327 , G06F9/3802 , G06F9/3804 , G06F9/3806 , G06F9/3826 , G06F9/3834 , G06F9/3836 , G06F9/3838 , G06F9/384 , G06F9/3851 , G06F9/3855 , G06F9/3857 , G06F9/3863 , G06F9/3865 , G06F9/3885
摘要： A high-performance, superscalar-based computer system with out-of-order instruction execution for enhanced resource utilization and performance throughput. The computer system fetches a plurality of fixed length instructions with a specified, sequential program order (in-order). The computer system includes an instruction execution unit including a register file, a plurality of functional units, and an instruction control unit for examining the instructions and scheduling the instructions for out-of-order execution by the functional units. The register file includes a set of temporary data registers that are utilized by the instruction execution control unit to receive data results generated by the functional units. The data results of each executed instruction are stored in the temporary data registers until all prior instructions have been executed, thereby retiring the executed instruction in-order.
摘要翻译：高性能，基于超标量的计算机系统，具有无序指令执行功能，可提高资源利用率和性能吞吐量。计算机系统以指定的顺序程序顺序（按顺序）获取多个固定长度指令。计算机系统包括指令执行单元，其包括寄存器文件，多个功能单元以及指令控制单元，用于检查指令并调度用于由功能单元执行无序执行的指令。寄存器文件包括一组由指令执行控制单元用于接收由功能单元产生的数据结果的临时数据寄存器。每个执行指令的数据结果存储在临时数据寄存器中，直到执行所有先前的指令为止，从而按顺序退出执行的指令。

2. 发明申请

US20060149925A1 High-performance superscalar-based computer system with out-of-order instruction execution and concurrent results distribution 失效
公开(公告)号：US20060149925A1
公开(公告)日：2006-07-06
申请号：US11316814
申请日：2005-12-27
申请人： Le Nguyen , Derek Lentz , Yoshiyuki Miyayama , Sanjiv Garg , Yasuaki Hagiwara , Johannes Wang , Te-Li Lau , Sze-Shun Wang , Quang Trang
发明人： Le Nguyen , Derek Lentz , Yoshiyuki Miyayama , Sanjiv Garg , Yasuaki Hagiwara , Johannes Wang , Te-Li Lau , Sze-Shun Wang , Quang Trang
IPC分类号： G06F15/00
CPC分类号： G06F9/30167 , G06F9/30054 , G06F9/30101 , G06F9/30105 , G06F9/30112 , G06F9/30116 , G06F9/3012 , G06F9/30123 , G06F9/3013 , G06F9/30134 , G06F9/30141 , G06F9/327 , G06F9/3802 , G06F9/3804 , G06F9/3814 , G06F9/3824 , G06F9/3828 , G06F9/3836 , G06F9/3838 , G06F9/384 , G06F9/3853 , G06F9/3857 , G06F9/3861 , G06F9/3865 , G06F9/3885
摘要： The high-performance, RISC core based microprocessor architecture includes an instruction fetch unit for fetching instruction sets from an instruction store and an execution unit that implements the concurrent execution of a plurality of instructions through a parallel array of functional units. The fetch unit generally maintains a predetermined number of instructions in an instruction buffer. The execution unit includes an instruction selection unit, coupled to the instruction buffer, for selecting instructions for execution, and a plurality of functional units for performing instruction specified functional operations. A unified instruction scheduler, within the instruction selection unit, initiates the processing of instructions through the functional units when instructions are determined to be available for execution and for which at least one of the functional units implementing a necessary computational function is available. Unified scheduling is performed across multiple execution data paths, where each execution data path, and corresponding functional units, is generally optimized for the type of computational function that is to be performed on the data: integer, floating point, and boolean. The number, type and computational specifics of the functional units provided in each data path, and as between data paths, are mutually independent.

3. 发明申请

US20070101103A1 High-performance superscalar-based computer system with out-of order instruction execution and concurrent results distribution 失效
标题翻译：高性能超标量计算机系统，具有无序指令执行和并发结果分配
公开(公告)号：US20070101103A1
公开(公告)日：2007-05-03
申请号：US11640967
申请日：2006-12-19
申请人： Le Nguyen , Derek Lentz , Yoshiyuki Miyayama , Sanjiv Garg , Yasuaki Hagiwara , Johannes Wang , Te-Li Lau , Sze-Shun Wang , Quang Trang
发明人： Le Nguyen , Derek Lentz , Yoshiyuki Miyayama , Sanjiv Garg , Yasuaki Hagiwara , Johannes Wang , Te-Li Lau , Sze-Shun Wang , Quang Trang
IPC分类号： G06F9/30
CPC分类号： G06F9/30167 , G06F9/30054 , G06F9/30101 , G06F9/30105 , G06F9/30112 , G06F9/30116 , G06F9/3012 , G06F9/30123 , G06F9/3013 , G06F9/30134 , G06F9/30141 , G06F9/327 , G06F9/3802 , G06F9/3804 , G06F9/3814 , G06F9/3824 , G06F9/3828 , G06F9/3836 , G06F9/3838 , G06F9/384 , G06F9/3853 , G06F9/3857 , G06F9/3861 , G06F9/3865 , G06F9/3885
摘要： The high-performance, RISC core based microprocessor architecture includes an instruction fetch unit for fetching instruction sets from an instruction store and an execution unit that implements the concurrent execution of a plurality of instructions through a parallel array of functional units. The fetch unit generally maintains a predetermined number of instructions in an instruction buffer. The execution unit includes an instruction selection unit, coupled to the instruction buffer, for selecting instructions for execution, and a plurality of functional units for performing instruction specified functional operations. A unified instruction scheduler, within the instruction selection unit, initiates the processing of instructions through the functional units when instructions are determined to be available for execution and for which at least one of the functional units implementing a necessary computational function is available. Unified scheduling is performed across multiple execution data paths, where each execution data path, and corresponding functional units, is generally optimized for the type of computational function that is to be performed on the data: integer, floating point, and boolean. The number, type and computational specifics of the functional units provided in each data path, and as between data paths, are mutually independent.
摘要翻译：高性能的基于RISC核心的微处理器架构包括用于从指令存储器取出指令集的指令获取单元和通过并行的功能单元阵列实现多个指令的并发执行的执行单元。提取单元通常在指令缓冲器中保持预定数量的指令。执行单元包括指令选择单元，耦合到指令缓冲器，用于选择用于执行的指令;以及多个功能单元，用于执行指令指定的功能操作。在指令选择单元内的统一指令调度器，当确定可用于执行的指令并且实现必要的计算功能的功能单元中的至少一个可用时，通过功能单元启动对指令的处理。在多个执行数据路径上执行统一调度，其中每个执行数据路径和相应的功能单元通常针对要在数据上执行的计算函数类型进行优化：整数，浮点和布尔值。在每个数据路径中以及数据路径之间提供的功能单元的数量，类型和计算细节是相互独立的。

4. 发明申请

US20050283591A1 System and method for handling load and/or store operations in a superscalar microprocessor 失效
公开(公告)号：US20050283591A1
公开(公告)日：2005-12-22
申请号：US11113135
申请日：2005-04-25
申请人： Cheryl Brashears , Johannes Wang , Le Nguyen , Derek Lentz , Yoshiyuki Miyayama , Sanjiv Garg , Yasuaki Hagiwara , Te-Li Lau , Sze-Shun Wang , Quang Trang
发明人： Cheryl Brashears , Johannes Wang , Le Nguyen , Derek Lentz , Yoshiyuki Miyayama , Sanjiv Garg , Yasuaki Hagiwara , Te-Li Lau , Sze-Shun Wang , Quang Trang
IPC分类号： G06F9/00 , G06F9/312 , G06F9/318 , G06F9/38
CPC分类号： G06F9/3004 , G06F9/30043 , G06F9/30087 , G06F9/3017 , G06F9/3834 , G06F9/3836 , G06F9/3838 , G06F9/3855 , G06F9/3857 , G06F9/3885
摘要： The present invention provides a system and method for managing load and store operations necessary for reading from and writing to memory or I/O in a superscalar RISC architecture environment. To perform this task, a load store unit is provided whose main purpose is to make load requests out of order whenever possible to get the load data back for use by an instruction execution unit as quickly as possible. A load operation can only be performed out of order if there are no address collisions and no write pendings. An address collision occurs when a read is requested at a memory location where an older instruction will be writing. Write pending refers to the case where an older instruction requests a store operation, but the store address has not yet been calculated. The data cache unit returns 8 bytes of unaligned data. The load/store unit aligns this data properly before it is returned to the instruction execution unit. Thus, the three main tasks of the load store unit are: (1) handling out of order cache requests; (2) detecting address collisions; and (3) alignment of data.

5. 发明申请

US20060064569A1 Microprocessor architecture capable of supporting multiple heterogeneous processors 失效
公开(公告)号：US20060064569A1
公开(公告)日：2006-03-23
申请号：US11213949
申请日：2005-08-30
申请人： Derek Lentz , Yasuaki Hagiwara , Te-Li Lau , Cheng-Long Tang , Le Nguyen
发明人： Derek Lentz , Yasuaki Hagiwara , Te-Li Lau , Cheng-Long Tang , Le Nguyen
IPC分类号： G06F15/76
CPC分类号： G06F12/0813 , G06F12/0215 , G06F12/0831 , G06F12/0855 , G06F13/18 , G06F13/4022 , G06F15/167 , G06F15/17 , G06F15/173
摘要： A memory control unit for controlling access, by one or more devices within a processor, to a memory array unit external to the processor via one or more memory ports of the processor. The memory control unit includes a switch network to transfer data between the one or more devices of the processor and the one or more memory ports of the processor. The memory control unit also includes a switch arbitration unit to arbitrate for the switch network, and a port arbitration unit to arbitrate for the one or more memory ports.

6. 发明申请

US20070113047A1 RISC microprocessor architecture implementing multiple typed register sets 失效
标题翻译： RISC微处理器架构实现多种类型的寄存器集
公开(公告)号：US20070113047A1
公开(公告)日：2007-05-17
申请号：US11651009
申请日：2007-01-09
申请人： Sanjiv Garg , Derek Lentz , Le Nguyen , Sho Chen
发明人： Sanjiv Garg , Derek Lentz , Le Nguyen , Sho Chen
IPC分类号： G06F15/76
CPC分类号： G06F9/30029 , G06F9/30036 , G06F9/30112 , G06F9/30116 , G06F9/3012 , G06F9/30123 , G06F9/3013 , G06F9/30138 , G06F9/30167 , G06F9/30189 , G06F9/3851
摘要： A register system for a data processor which operates in a plurality of modes. The register system provides multiple, identical banks of register sets, the data processor controlling access such that instructions and processes need not specify any given bank. An integer register set includes first (RA[23:0]) and second (RA[31:24]) subsets, and a shadow subset (RT[31:24]). While the data processor is in a first mode, instructions access the first and second subsets. While the data processor is in a second mode, instructions may access the first subset, but any attempts to access the second subset are re-routed to the shadow subset instead, transparently to the instructions, allowing system routines to seemingly use the second subset without having to save and restore data which user routines have written to the second subset. A re-typable register set provides integer width data and floating point width data in response to integer instructions and floating point instructions, respectively. Boolean comparison instructions specify particular integer or floating point registers for source data to be compared, and specify a particular Boolean register for the result, so there are no dedicated, fixed-location status flags. Boolean combinational instructions combine specified Boolean registers, for performing complex Boolean. comparisons without intervening conditional branch instructions, to minimize pipeline disruption.
摘要翻译：一种用于以多种模式操作的数据处理器的寄存器系统。寄存器系统提供多个相同的寄存器组，数据处理器控制访问，使得指令和过程不需要指定任何给定的存储体。整数寄存器集包括第一（RA [23：0]）和第二（RA [31:24]）子集和影子子集（RT [31:24]）。当数据处理器处于第一模式时，指令访问第一和第二子集。当数据处理器处于第二模式时，指令可以访问第一子集，但是任何访问第二子集的尝试都被重新路由到阴影子集，而不是透明地指向该指令，从而允许系统例程看起来使用第二子集，而没有必须保存和恢复哪个用户例程已写入第二个子集的数据。重分类寄存器组分别提供整数宽度数据和浮点宽度数据，以响应整数指令和浮点指令。布尔比较指令为要比较的源数据指定特定的整数或浮点寄存器，并为结果指定一个特定的布尔寄存器，因此没有专用的固定位置状态标志。布尔组合指令组合指定的布尔寄存器，用于执行复杂布尔值。比较没有干预条件分支指令，以最大限度地减少管道中断。

7. 发明申请

US20080059770A1 Superscalar RISC instruction scheduling 失效
标题翻译：超标量RISC指令调度
公开(公告)号：US20080059770A1
公开(公告)日：2008-03-06
申请号：US11730566
申请日：2007-04-02
申请人： Sanjiv Garg , Kevin Iadonato , Le Nguyen , Johannes Wang
发明人： Sanjiv Garg , Kevin Iadonato , Le Nguyen , Johannes Wang
IPC分类号： G06F9/312
CPC分类号： G06F9/3013 , G06F9/3824 , G06F9/3838 , G06F9/384 , G06F9/3855
摘要： A register renaming system for out-of-order execution of a set of reduced instruction set computer instructions having addressable source and destination register fields, adapted for use in a computer having an instruction execution unit with a register file accessed by read address ports and for storing instruction operands. A data dependance check circuit is included for determining data dependencies between the instructions. A tag assignment circuit generates one or more tags to specify the location of operands, based on the data dependencies determined by the data dependance check circuit. A set of register file port multiplexers select the tags generated by the tag assignment circuit and pass the tags onto the read address ports of the register file for storing execution results.
摘要翻译：一种用于无序执行一组具有可寻址源和目的寄存器字段的精简指令集计算机指令的寄存器重命名系统，适用于具有指令执行单元的计算机，该指令执行单元具有通过读地址端口访问的寄存器文件，存储指令操作数。包括数据相关性检查电路，用于确定指令之间的数据依赖性。标签分配电路基于由数据相关性检查电路确定的数据依赖性，生成一个或多个标签以指定操作数的位置。一组寄存器文件端口复用器选择标签分配电路产生的标签，并将标签传递到寄存器文件的读取地址端口，以存储执行结果。

8. 发明申请

US20060041736A1 Superscalar RISC instruction scheduling 审中-公开
公开(公告)号：US20060041736A1
公开(公告)日：2006-02-23
申请号：US11252820
申请日：2005-10-19
申请人： Sanjiv Garg , Kevin Iadonato , Le Nguyen , Johannes Wang
发明人： Sanjiv Garg , Kevin Iadonato , Le Nguyen , Johannes Wang
IPC分类号： G06F15/76 , G06F15/00
CPC分类号： G06F9/3013 , G06F9/3824 , G06F9/3838 , G06F9/384 , G06F9/3855
摘要： A register renaming system for out-of-order execution of a set of reduced instruction set computer instructions having addressable source and destination register fields, adapted for use in a computer having an instruction execution unit with a register file accessed by read address ports and for storing instruction operands. A data dependance check circuit is included for determining data dependencies between the instructions. A tag assignment circuit generates one or more tags to specify the location of operands, based on the data dependencies determined by the data dependance check circuit. A set of register file port multiplexers select the tags generated by the tag assignment circuit and pass the tags onto the read address ports of the register file for storing execution results.

9. 发明授权

US6003129A System and method for handling interrupt and exception events in an asymmetric multiprocessor architecture 失效
标题翻译：用于处理非对称多处理器架构中的中断和异常事件的系统和方法
公开(公告)号：US6003129A
公开(公告)日：1999-12-14
申请号：US699294
申请日：1996-08-19
申请人： Seungyeon Peter Song , Moataz A. Mohamed , Heon-Chul Park , Le Nguyen
发明人： Seungyeon Peter Song , Moataz A. Mohamed , Heon-Chul Park , Le Nguyen
IPC分类号： G06F9/46 , G06F7/544 , G06F9/48 , G06F15/16 , G06F15/17 , G06F17/16 , G06F17/00
CPC分类号： G06F7/5443 , G06F15/17
摘要： A multiprocessor computer system includes a plurality of processors, called asymmetric processors, having mutually dissimilar control and data-handling characteristics. The asymmetric processors are controlled by a single operating system although the individual processors have instruction sets that are mutually independent of the other processors. The multiprocessor computer system uses a multiprocessor architectural definition of interrupt and exception handling in which a processor, called a data or vector processor, having a large machine state and a large data width detects exceptions but defers interrupt and exception handling operations to another processor, called a control processor, having a small machine state and data width. The small machine state and small data width of the control processor are well suited for executing operating system programs such as interrupt and exception handling since control programs typically involve monitoring and control of individual flags and pointers. The data processor enters an idle state upon reset and when an exception is detected to facilitate system design and programming, and to simplify synchronization of the processors at system reset. A multiprocessor computer system includes a control processor which reads and writes control and status registers within a data processor. The control processor thus controls the operation of the data processor during execution of an operating system or application programs. The control processor has access to the control and status registers of the data processor independent of the data processor execution so that the same control and status registers may be accessed by the control processor and the data processor in parallel.
摘要翻译：多处理器计算机系统包括称为非对称处理器的多个处理器，具有相互不同的控制和数据处理特性。非对称处理器由单个操作系统控制，尽管各个处理器具有彼此独立于其他处理器的指令集。多处理器计算机系统使用中断和异常处理的多处理器体系结构定义，其中具有大机器状态和大数据宽度的称为数据或向量处理器的处理器检测异常，但是将中断和异常处理操作阻止到另一个处理器，称为控制处理器，具有小的机器状态和数据宽度。控制处理器的小机器状态和小数据宽度非常适合于执行诸如中断和异常处理之类的操作系统程序，因为控制程序通常涉及监视和控制各个标志和指针。数据处理器在复位时进入空闲状态，并且当检测到异常以便于系统设计和编程时，并且在系统复位时简化处理器的同步。多处理器计算机系统包括在数据处理器内读取和写入控制和状态寄存器的控制处理器。因此，控制处理器在操作系统或应用程序的执行期间控制数据处理器的操作。控制处理器可独立于数据处理器的执行访问数据处理器的控制和状态寄存器，使得控制处理器和数据处理器可以并行地访问相同的控制和状态寄存器。

10. 发明申请

US20130132882A1 MODULAR CHEMISTRY ANALYZER 审中-公开
标题翻译：模块化学分析仪
公开(公告)号：US20130132882A1
公开(公告)日：2013-05-23
申请号：US13618429
申请日：2012-09-14
申请人： Jeannine Dussi , Edward Gunshirt , Ray Goodwin , Stan Liffmann , Tony Mao , Doug Moe , Steve Rettew , Ian Smith , Charlene Soley , Le Nguyen , Qian Sun , Will Whelan , Diana Zipeto , Gregory Sweetser
发明人： Jeannine Dussi , Edward Gunshirt , Ray Goodwin , Stan Liffmann , Tony Mao , Doug Moe , Steve Rettew , Ian Smith , Charlene Soley , Le Nguyen , Qian Sun , Will Whelan , Diana Zipeto , Gregory Sweetser
IPC分类号： G06F3/0481
CPC分类号： G06K19/0723 , G01N35/00722 , G01N35/025 , G01N35/10 , G01N2035/00326 , G06F3/04817 , Y10T436/11 , Y10T436/114165
摘要： Disclosed in one general aspect is a method of operating a chemistry analyzer method that includes determining usage levels associated with a plurality of storage vessels that store reagents for use by the analyzer. A pictorial representation that includes a plurality of graphical elements that convey levels of usage for the storage vessels is displayed to the operator. A series of access icons that are each associated with a color and each lead to a set of screens for different types of operations for the analyzer are also displayed, with the screens being color coded to correspond to the color associated with their respective access icons.
摘要翻译：公开的一个一般方面是一种操作化学分析仪方法的方法，该方法包括确定与多个储存容器相关联的使用水平，所述存储容器存储试剂供分析仪使用。向操作员显示包括传达存储容器的使用级别的多个图形元素的图形表示。还显示了一系列与颜色相关联的访问图标，每个访问图标通向用于分析器的不同类型的操作的一组屏幕，其中屏幕被颜色编码以对应于与其各自的访问图标相关联的颜色。

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