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    • 2. 发明申请
    • Embedded waveguide detectors
    • 嵌入式波导检测器
    • US20070018270A1
    • 2007-01-25
    • US11484009
    • 2006-07-10
    • Francisco LeonLawrence WestYuichi WadaGregory WojcikStephen Moffatt
    • Francisco LeonLawrence WestYuichi WadaGregory WojcikStephen Moffatt
    • H01L31/00
    • G02B6/12004G02B2006/12061H01L31/0232H01L31/0288H01L31/105H01L31/1812Y02E10/50
    • A method of fabricating a detector that involves: forming a trench in a substrate, the substrate having an upper surface; forming a first doped semiconductor layer on the substrate and in the trench; forming a second semiconductor layer on the first doped semiconductor layer and extending into the trench, the second semiconductor layer having a conductivity that is less than the conductivity of the first doped semiconductor layer; forming a third doped semiconductor layer on the second semiconductor layer and extending into the trench; removing portions of the first, second and third layers that are above a plane defined by the surface of the substrate to produce an upper, substantially planar surface and expose an upper end of the first doped semiconductor layer in the trench; forming a first electrical contact to the first semiconductor doped layer; and forming a second electrical contact to the third semiconductor doped layer.
    • 一种制造检测器的方法,包括:在衬底中形成沟槽,所述衬底具有上表面; 在所述衬底和所述沟槽中形成第一掺杂半导体层; 在所述第一掺杂半导体层上形成第二半导体层并延伸到所述沟槽中,所述第二半导体层的导电率小于所述第一掺杂半导体层的导电性; 在所述第二半导体层上形成第三掺杂半导体层并延伸到所述沟槽中; 去除在由衬底的表面限定的平面之上的第一层,第二层和第三层的部分,以产生上部基本平坦的表面,并且暴露沟槽中的第一掺杂半导体层的上端; 形成第一电接触到第一半导体掺杂层; 以及向所述第三半导体掺杂层形成第二电接触。
    • 4. 发明申请
    • Embedded waveguide detectors
    • 嵌入式波导检测器
    • US20050051767A1
    • 2005-03-10
    • US10856750
    • 2004-05-28
    • Francisco LeonLawrence WestYuichi WadaGregory WojcikStephen Moffatt
    • Francisco LeonLawrence WestYuichi WadaGregory WojcikStephen Moffatt
    • G02B20060101G02B6/12H01L29/06H01L31/0232
    • G02B6/12004G02B2006/12061H01L31/0232H01L31/0288H01L31/105H01L31/1812Y02E10/50
    • A method of fabricating a detector that involves: forming a trench in a substrate, the substrate having an upper surface; forming a first doped semiconductor layer on the substrate and in the trench; forming a second semiconductor layer on the first doped semiconductor layer and extending into the trench, the second semiconductor layer having a conductivity that is less than the conductivity of the first doped semiconductor layer; forming a third doped semiconductor layer on the second semiconductor layer and extending into the trench; removing portions of the first, second and third layers that are above a plane defined by the surface of the substrate to produce an upper, substantially planar surface and expose an upper end of the first doped semiconductor layer in the trench; forming a first electrical contact to the first semiconductor doped layer; and forming a second electrical contact to the third semiconductor doped layer.
    • 一种制造检测器的方法,包括:在衬底中形成沟槽,所述衬底具有上表面; 在所述衬底和所述沟槽中形成第一掺杂半导体层; 在所述第一掺杂半导体层上形成第二半导体层并延伸到所述沟槽中,所述第二半导体层的导电率小于所述第一掺杂半导体层的导电性; 在所述第二半导体层上形成第三掺杂半导体层并延伸到所述沟槽中; 去除在由衬底的表面限定的平面之上的第一层,第二层和第三层的部分,以产生上部基本平坦的表面,并且暴露沟槽中的第一掺杂半导体层的上端; 形成第一电接触到第一半导体掺杂层; 以及向所述第三半导体掺杂层形成第二电接触。
    • 5. 发明申请
    • Sige super lattice optical detectors
    • 超晶格光学检测仪
    • US20050214964A1
    • 2005-09-29
    • US10959599
    • 2004-10-06
    • Lawrence WestFrancisco Leon
    • Lawrence WestFrancisco Leon
    • H01L21/00H01L29/739H01L31/0328H01L31/0336H01L31/0352H01L31/072H01L31/103H01L31/109H01L31/18
    • H01L31/03529B82Y20/00H01L31/035254H01L31/035281H01L31/1037H01L31/1812Y02E10/50
    • An optical detector including a substrate; an island of detector material formed on the substrate, the island being a stack extending up from the substrate of alternating layers of first and second semiconductor materials, the island having a horizontally oriented top end, a vertically oriented first sidewall, and vertically oriented second sidewall that is opposite the first sidewall, the island having a first doped region extending into the island through first sidewall and forming a first conductive region that extends down into the island of detector material, the island also having a second doped region extending into the island through the second sidewall and forming a second conductive region that extends down into island of the detector material, the first and second conductive regions each having a top end that is part of the top end of the island; a first electrical connection to the top end of the first conductive region; and a second electrical connection to the top end of the second conductive region.
    • 一种包括基板的光学检测器; 形成在基板上的检测器材料的岛,该岛是从第一和第二半导体材料的交替层的衬底向上延伸的堆,该岛具有水平取向的顶端,垂直取向的第一侧壁和垂直取向的第二侧壁 所述岛具有通过第一侧壁延伸到岛中的第一掺杂区域,并且形成向下延伸到探测器材料岛的第一导电区域,该岛还具有延伸到岛中的第二掺杂区域 所述第二侧壁并形成向下延伸到所述检测器材料岛的第二导电区域,所述第一和第二导电区域各自具有作为所述岛的顶端的一部分的顶端; 与所述第一导电区域的顶端的第一电连接; 以及到第二导电区域的顶端的第二电连接。
    • 8. 发明申请
    • Self-aligned implanted waveguide detector
    • 自对准植入波导检测器
    • US20050212068A1
    • 2005-09-29
    • US10959897
    • 2004-10-06
    • Francisco LeonLawrence West
    • Francisco LeonLawrence West
    • H01L27/14
    • H01L31/035254B82Y20/00G02B6/12004
    • A method of fabricating a detector, the method including forming an island of detector core material on a substrate, the island having a horizontally oriented top end, a vertically oriented first sidewall, and a vertically oriented second sidewall that is opposite said first sidewall; implanting a first dopant into the first sidewall to form a first conductive region that has a top end that is part of the top end of the island; implanting a second dopant into the second sidewall to form a second conductive region that has a top end that is part of the top end of the island; fabricating a first electrical connection to the top end of the first conductive region; and fabricating a second electrical connection to the top end of the second conductive region.
    • 一种制造检测器的方法,所述方法包括在衬底上形成检测器芯材料岛,所述岛具有水平取向的顶端,垂直取向的第一侧壁和与所述第一侧壁相对的垂直取向的第二侧壁; 将第一掺杂剂注入到所述第一侧壁中以形成具有作为所述岛的顶端的一部分的顶端的第一导电区域; 将第二掺杂剂注入所述第二侧壁中以形成具有作为所述岛的顶端的一部分的顶端的第二导电区域; 制造到第一导电区域的顶端的第一电连接; 以及制造到所述第二导电区域的顶端的第二电连接。