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1. 发明申请

US20080062807A1 MULTI-COLUMN ADDRESSING MODE MEMORY SYSTEM INCLUDING AN INTEGRATED CIRCUIT MEMORY DEVICE 有权
标题翻译：包括集成电路存储器件的多字段寻址模式存储器系统
公开(公告)号：US20080062807A1
公开(公告)日：2008-03-13
申请号：US11853708
申请日：2007-09-11
申请人： Frederick Ware , Lawrence Lai , Chad Bellows , Wayne Richardson
发明人： Frederick Ware , Lawrence Lai , Chad Bellows , Wayne Richardson
IPC分类号： G11C8/00
CPC分类号： G11C8/10 , G11C8/12 , G11C8/16
摘要： A memory system includes a master device, such as a graphics controller or processor, and an integrated circuit memory device operable in a dual column addressing mode. The integrated circuit memory device includes an interface and column decoder to access a row of storage cells or a page in a memory bank. During a first mode of operation, a first row of storage cells in a first memory bank is accessible in response to a first column address. During a second mode of operation, a first plurality of storage cells in the first row of storage cells is accessible in response to a second column address during a column cycle time interval. A second plurality of storage cells in the first row of storage cells is accessible in response to a third column address during the column cycle time interval. The first and second pluralities of storage cells are concurrently accessible from the interface.
摘要翻译：存储器系统包括主设备，诸如图形控制器或处理器，以及以双列寻址模式可操作的集成电路存储器件。集成电路存储器件包括一个接口和列解码器，以访问一行存储单元或存储体中的一页。在第一操作模式期间，响应于第一列地址可访问第一存储体中的第一行存储单元。在第二操作模式期间，响应于列周期时间间隔期间的第二列地址，可访问第一行存储单元中的第一多个存储单元。响应于列周期时间间隔期间的第三列地址，可访问第一行存储单元中的第二多个存储单元。第一和第二多个存储单元可以从该接口同时访问。

2. 发明授权

US06754120B1 DRAM output circuitry supporting sequential data capture to reduce core access times 失效
标题翻译： DRAM输出电路支持顺序数据采集，以减少核心访问时间
公开(公告)号：US06754120B1
公开(公告)日：2004-06-22
申请号：US10364178
申请日：2003-02-11
申请人： Chad Bellows , Wayne Richardson , Lawrence Lai , Kurt Knorpp
发明人： Chad Bellows , Wayne Richardson , Lawrence Lai , Kurt Knorpp
IPC分类号： G11C700
CPC分类号： G11C7/1051 , G11C7/06 , G11C7/1012 , G11C7/106 , G11C7/1066 , G11C7/1069 , G11C11/4096
摘要： Described are memory systems designed to emphasize differences between memory-cell access times. As a consequence of these access-time variations, data read from different memory cells arrives at some modified output circuitry. The output circuitry sequentially offloads the data in the order of arrival. Data access times are reduced because the output circuitry can begin shifting the first data to arrive before the slower data is ready for capture. Differences between data access times for cells in a given memory array may be emphasized using differently sized sense amplifiers, routing, or both.
摘要翻译：描述了旨在强调存储单元访问时间之间的差异的存储器系统。作为这些访问时间变化的结果，从不同存储器单元读取的数据到达一些修改的输出电路。输出电路按顺序卸载数据。数据访问时间减少，因为输出电路可以在较慢的数据准备好捕捉之前开始移位第一个数据到达。可以使用不同大小的读出放大器，路由或两者来强调给定存储器阵列中的单元的数据访问时间之间的差异。

3. 发明申请

US20060117155A1 Micro-threaded memory 有权
公开(公告)号：US20060117155A1
公开(公告)日：2006-06-01
申请号：US10998402
申请日：2004-11-29
申请人： Frederick Ware , Craig Hampel , Wayne Richardson , Chad Bellows , Lawrence Lai
发明人： Frederick Ware , Craig Hampel , Wayne Richardson , Chad Bellows , Lawrence Lai
IPC分类号： G06F12/14
CPC分类号： G06F3/0659 , G06F3/0613 , G06F3/0673 , G11C7/1006 , G11C7/1042 , G11C7/22 , G11C8/06 , G11C11/4076 , G11C11/4097
摘要： A micro-threaded memory device. A plurality of storage banks are provided, each including a plurality of rows of storage cells and having an access restriction in that at least a minimum access time interval must transpire between successive accesses to a given row of the storage cells. Transfer control circuitry is provided to transfer a first amount of data between the plurality of storage banks and an external signal path in response to a first memory access request, the first amount of data being less than a product of the external signal path bandwidth and the minimum access time interval.

4. 发明申请

US20060072366A1 Multi-column addressing mode memory system including an integrated circuit memory device 有权
标题翻译：多列寻址模式存储器系统，包括集成电路存储器件
公开(公告)号：US20060072366A1
公开(公告)日：2006-04-06
申请号：US10955193
申请日：2004-09-30
申请人： Frederick Ware , Lawrence Lai , Chad Bellows , Wayne Richardson
发明人： Frederick Ware , Lawrence Lai , Chad Bellows , Wayne Richardson
IPC分类号： G11C8/00
CPC分类号： G11C8/10 , G11C8/12 , G11C8/16
摘要： A memory system includes a master device, such as a graphics controller or processor, and an integrated circuit memory device operable in a dual column addressing mode. The integrated circuit memory device includes an interface and column decoder to access a row of storage cells or a page in a memory bank. During a first mode of operation, a first row of storage cells in a first memory bank is accessible in response to a first column address. During a second mode of operation, a first plurality of storage cells in the first row of storage cells is accessible in response to a second column address during a column cycle time interval. A second plurality of storage cells in the first row of storage cells is accessible in response to a third column address during the column cycle time interval. During a third mode of operation, a first plurality of storage cells in a first row of storage cells in a first memory bank is accessible in response to a first column address. A second plurality of storage cells in a second row of storage cells in a second bank is accessible in response to a second column address. A third plurality of storage cells in the first row of storage cells is accessible in response to a third column address and a fourth plurality of storage cells in the second row of storage cells is accessible in response to a fourth column address. The first and second column addresses are in a first request packet and the third and fourth column addresses are in a second request packet provided by the master device.
摘要翻译：存储器系统包括主设备，诸如图形控制器或处理器，以及以双列寻址模式可操作的集成电路存储器件。集成电路存储器件包括一个接口和列解码器，以访问一行存储单元或存储体中的一页。在第一操作模式期间，响应于第一列地址可访问第一存储体中的第一行存储单元。在第二操作模式期间，响应于列周期时间间隔期间的第二列地址，可访问第一行存储单元中的第一多个存储单元。响应于列周期时间间隔期间的第三列地址，可访问第一行存储单元中的第二多个存储单元。在第三操作模式期间，响应于第一列地址可访问第一存储体中的第一行存储单元中的第一多个存储单元。响应于第二列地址，可访问第二存储体中第二行存储单元中的第二多个存储单元。第一行存储单元中的第三多个存储单元响应于第三列地址而可访问，并且第二行存储单元中的第四多个存储单元响应于第四列地址而可访问。第一列地址和第二列地址在第一请求分组中，并且第三和第四列地址在由主设备提供的第二请求分组中。

5. 发明申请

US20070250677A1 Multi-Mode Memory 审中-公开
标题翻译：多模式存储器
公开(公告)号：US20070250677A1
公开(公告)日：2007-10-25
申请号：US11767863
申请日：2007-06-25
申请人： Frederick Ware , Craig Hampel , Wayne Richardson , Chad Bellows , Lawrence Lai
发明人： Frederick Ware , Craig Hampel , Wayne Richardson , Chad Bellows , Lawrence Lai
IPC分类号： G06F13/372
CPC分类号： G06F3/0659 , G06F3/0613 , G06F3/0673 , G11C7/1006 , G11C7/1042 , G11C7/22 , G11C8/06 , G11C11/4076 , G11C11/4097
摘要： A multi-mode memory device. A plurality of storage banks are provided, each including a plurality of rows of storage cells and having an access restriction in that at least a minimum access time interval is imposed between successive accesses to a given row of the storage cells. Data path circuitry is provided to transfer data between the plurality of storage banks and an external signal path during first and second modes of operation of the memory device. During the first mode of operation a first data item is transferred, in response to a first memory access request, during a first time interval that is not longer than the minimum time interval. During the second mode of operation a plurality of data items are transferred during the first time interval, in response to a plurality of memory access requests.
摘要翻译：多模式存储器件。提供了多个存储体，每个存储体包括多行存储单元并且具有访问限制，因为在对存储单元的给定行的连续访问之间至少施加最小访问时间间隔。提供数据路径电路以在存储器件的第一和第二操作模式期间在多个存储体之间传送数据和外部信号路径。在第一操作模式期间，响应于第一存储器访问请求，在不长于最小时间间隔的第一时间间隔期间传送第一数据项。在第二操作模式期间，响应于多个存储器访问请求，在第一时间间隔期间传送多个数据项。

6. 发明申请

US20060039227A1 Memory device having staggered memory operations 有权
标题翻译：具有交错存储器操作的存储器件
公开(公告)号：US20060039227A1
公开(公告)日：2006-02-23
申请号：US10920508
申请日：2004-08-17
申请人： Lawrence Lai , Wayne Richardson , Chad Bellows
发明人： Lawrence Lai , Wayne Richardson , Chad Bellows
IPC分类号： G11C7/10
CPC分类号： G11C7/1042 , G11C7/22 , G11C8/12 , G11C2207/2227
摘要： A memory system includes logical banks divided into sub-banks or collections of sub-banks. The memory system responds to memory-access requests (e.g., read and write) directed to a given logical bank by sequentially accessing sub-banks or collections of sub-banks. Sequential access reduces the impact of power-supply spikes induced by memory operations, and thus facilitates improved system performance. Some embodiments of the memory system combine sequential sub-bank access with other performance-enhancing features, such as wider power buses or increased bypass capacitance, to further enhance performance.
摘要翻译：记忆系统包括分为子银行或子银行集合的逻辑银行。存储器系统通过顺序地访问子银行或子银行集合来响应指向给定逻辑银行的存储器访问请求（例如，读取和写入）。顺序访问减少了由存储器操作引起的电源尖峰的影响，从而有助于提高系统性能。存储器系统的一些实施例将顺序的子银行访问与诸如更宽的电源总线或增加的旁路电容的其他性能增强特征相结合，以进一步提高性能。

7. 发明申请

US20070268765A1 Integrated Circuit Memory Device Having Dynamic Memory Bank Count and Page Size 有权
标题翻译：具有动态存储器计数和页面大小的集成电路存储器件
公开(公告)号：US20070268765A1
公开(公告)日：2007-11-22
申请号：US11834915
申请日：2007-08-07
申请人： Steven Woo , Michael Ching , Chad Bellows , Wayne Richardson , Kurt Knorpp , Jun Kim
发明人： Steven Woo , Michael Ching , Chad Bellows , Wayne Richardson , Kurt Knorpp , Jun Kim
IPC分类号： G11C7/02
CPC分类号： G11C7/106 , G11C7/065 , G11C7/1045 , G11C7/1051
摘要： An integrated circuit memory device has a storage array with an adjustable number of memory banks, a row of sense amplifiers to access storage cells in the storage array; and memory access control circuitry. The memory access control circuitry provides a first number of memory banks and a first page size in the integrated circuit memory device in a first mode of operation, and provides a second number of memory banks and a second page size in the integrated circuit memory device in a second mode of operation. The memory access control circuitry includes logic circuitry to adjust the number of memory banks in the integrated circuit memory device, and to adjust the page size of the integrated circuit memory device.
摘要翻译：集成电路存储器件具有可调节数量的存储体的存储阵列，一行读出放大器，用于存取存储阵列中的存储单元; 和存储器访问控制电路。存储器访问控制电路在第一操作模式下在集成电路存储器件中提供第一数量的存储体和第一页面大小，并且在集成电路存储器件中提供第二数量的存储体和第二页面尺寸第二种操作模式。存储器访问控制电路包括用于调整集成电路存储器件中的存储体的数量的逻辑电路，并且调整集成电路存储器件的页面大小。

8. 发明申请

US20060067146A1 Integrated circuit memory system having dynamic memory bank count and page size 有权
标题翻译：具有动态存储体积和页面大小的集成电路存储器系统
公开(公告)号：US20060067146A1
公开(公告)日：2006-03-30
申请号：US10954941
申请日：2004-09-30
申请人： Steven Woo , Michael Ching , Chad Bellows , Wayne Richardson , Kurt Knorpp , Jun Kim
发明人： Steven Woo , Michael Ching , Chad Bellows , Wayne Richardson , Kurt Knorpp , Jun Kim
IPC分类号： G11C7/02
CPC分类号： G11C7/106 , G11C7/065 , G11C7/1045 , G11C7/1051
摘要： A memory system includes a master device, such as a graphics controller or processor, and an integrated circuit memory device operable in dynamic memory bank count and page size mode. The integrated circuit memory device includes a first and second row of storage cells coupled to a row of sense amplifiers including a first and second plurality of sense amplifiers. During the first mode of operation, a first plurality of data is transferred from the first plurality of storage cells to the row of sense amplifiers. During the second mode of operation, a second plurality of data is transferred from the first row of storage cells to the first plurality of sense amplifiers and a third plurality of data is transferred from the second row of storage cells to the second plurality of sense amplifiers. The second and third plurality of data is accessible simultaneously from the memory device interface during the second mode of operation. In an embodiment, the second plurality of data is transferred from the first half of the first row and the third plurality of data is transferred from the second half of the second row.
摘要翻译：存储器系统包括主设备，诸如图形控制器或处理器，以及可以动态存储器库计数和页大小模式操作的集成电路存储器件。集成电路存储器件包括耦合到包括第一和第二多个读出放大器的读出放大器行的第一和第二行存储单元。在第一操作模式期间，第一多个数据从第一多个存储单元传送到读出放大器行。在第二操作模式期间，第二多个数据从第一行存储单元转移到第一多个读出放大器，并且第三多个数据从第二行存储单元传送到第二多个读出放大器。在第二操作模式期间，第二和第三多个数据可以从存储器设备接口同时访问。在一个实施例中，第二多个数据从第一行的前半部分传送，第三个数据从第二行的后半部分传送。

9. 发明申请

US20070214335A1 Memory device with mode-selectable prefetch and clock-to-core timing 失效
标题翻译：具有模式可选预取和时钟到核心定时的存储器件
公开(公告)号：US20070214335A1
公开(公告)日：2007-09-13
申请号：US11373394
申请日：2006-03-10
申请人： Chad Bellows , Craig Hampel
发明人： Chad Bellows , Craig Hampel
IPC分类号： G06F13/00
CPC分类号： G11C7/1039 , G11C7/1012 , G11C7/1042 , G11C7/1051 , G11C7/1066 , G11C2207/107
摘要： In a memory device, either a first portion or a second, smaller portion of data retrieved from a storage array is loaded into a data buffer in accordance with a prefetch mode selection and then output from the memory device via a signaling interface. A value that indicates a minimum number of cycles of a clock signal that are to transpire between successive accesses to any one of the storage resources may be received and stored within a configuration circuit of the memory device. If the value indicates a number of clock cycles, N, that is less than a threshold number, the memory device may transfer data associated with a first address between the signaling interface and the data buffer during each of N cycles of the clock signal. If N is greater than or equal to the threshold number, the memory device may transfer the data associated with the first address between the signaling interface and the storage buffer during each of X cycles of the clock signal, and then transfer data associated with the second address between the signaling interface and the storage buffer during each of X cycles of the clock signal, where X is an integer value less than N.
摘要翻译：在存储器件中，根据预取模式选择将从存储阵列检索的数据的第一部分或第二较小部分的数据加载到数据缓冲器中，然后经由信令接口从存储器件输出。指示在对任何一个存储资源的连续访问之间发生的时钟信号的最小周期数的值可以被接收并存储在存储器件的配置电路中。如果该值指示小于阈值数目的时钟周期数N，则存储器件可以在时钟信号的N个周期的每个周期期间传送与信令接口和数据缓冲器之间的第一地址相关联的数据。如果N大于或等于阈值数，则在时钟信号的X个周期的每个周期期间，存储器件可以传送与信号接口和存储缓冲器之间的第一地址相关联的数据，然后传送与第二个在时钟信号的X个周期的每个周期期间，信令接口和存储缓冲器之间的地址，其中X是小于N的整数值。

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