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1. 发明授权

US5304860A Method for powering down a microprocessor embedded within a gate array 失效
标题翻译：为嵌入在门阵列内的微处理器断电的方法
公开(公告)号：US5304860A
公开(公告)日：1994-04-19
申请号：US135637
申请日：1993-10-12
申请人： Laurin R. Ashby , Franz Steininger
发明人： Laurin R. Ashby , Franz Steininger
IPC分类号： G06F15/78 , H01L21/82 , H01L27/118 , H03K19/177
CPC分类号： G06F15/7867
摘要： An interface circuit (14) that allows for a flexible three-way interface between a microprocessor (12), an ASIC cell block (16), and the external world has been provided wherein the microprocessor and the ASIC cell block are fabricated within a gate array (10). The interface circuit provides circuitry for each I/O pin (22, 23, 24) of the microprocessor to allow it to readily interface with the customer designed ASIC cell block or external devices via the ASIC I/O pads (20). The interface circuit also allows isolated testing of only the microprocessor, of only the ASIC cell block, or of both the microprocessor and the ASIC cell block. The interface circuit and the microprocessor are fully diffused and fixed-placed within the gate array while the ASIC cell block may be utilized by a customer to design a circuit to perform a customer defined function.
摘要翻译：已经提供了允许微处理器（12），ASIC单元块（16）和外部世界之间的灵活三向接口的接口电路（14），其中微处理器和ASIC单元块被制造在门数组（10）。接口电路为微处理器的每个I / O引脚（22,23,24）提供电路，以允许其通过ASIC I / O焊盘（20）容易地与客户设计的ASIC单元块或外部设备进行接口。接口电路还允许仅对ASIC单元块或微处理器和ASIC单元块的微处理器进行隔离测试。接口电路和微处理器完全扩散并固定在门阵列内，而ASIC单元块可由客户利用来设计电路以执行客户定义的功能。

2. 发明授权

US5347181A Interface control logic for embedding a microprocessor in a gate array 失效
标题翻译：用于将微处理器嵌入门阵列的接口控制逻辑
公开(公告)号：US5347181A
公开(公告)日：1994-09-13
申请号：US875508
申请日：1992-04-29
申请人： Laurin R. Ashby , Franz Steininger
发明人： Laurin R. Ashby , Franz Steininger
IPC分类号： G06F15/78 , H01L21/82 , H01L27/118 , H03K19/177
CPC分类号： G06F15/7867
摘要： An interface circuit (14) that allows for a flexible three-way interface between a microprocessor (12), an ASIC cell block (16), and the external world has been provided wherein the microprocessor and the ASIC cell block are fabricated within a gate array (10). The interface circuit provides circuitry for each I/O pin (22, 23, 24) of the microprocessor to allow it to readily interface with the customer designed ASIC cell block or external devices via the ASIC I/O pads (20). The interface circuit also allows isolated testing of only the microprocessor, of only the ASIC cell block, or of both the microprocessor and the ASIC cell block. The interface circuit and the microprocessor are fully diffused and fixed-placed within the gate array while the ASIC cell block may be utilized by a customer to design a circuit to perform a customer defined function.
摘要翻译：已经提供了允许微处理器（12），ASIC单元块（16）和外部世界之间的灵活三向接口的接口电路（14），其中微处理器和ASIC单元块被制造在门数组（10）。接口电路为微处理器的每个I / O引脚（22,23,24）提供电路，以允许其通过ASIC I / O焊盘（20）容易地与客户设计的ASIC单元块或外部设备进行接口。接口电路还允许仅对ASIC单元块或微处理器和ASIC单元块的微处理器进行隔离测试。接口电路和微处理器完全扩散并固定在门阵列内，而ASIC单元块可由客户利用来设计电路以执行客户定义的功能。

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