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1. 发明授权

US09191598B2 Front-end pixel fixed pattern noise correction in imaging arrays having wide dynamic range 有权
标题翻译：具有宽动态范围的成像阵列中的前端像素固定图案噪声校正
公开(公告)号：US09191598B2
公开(公告)日：2015-11-17
申请号：US13206175
申请日：2011-08-09
申请人： Laurent Blanquart , Ying Huang , Joey Shah , David Lawrence Standley
发明人： Laurent Blanquart , Ying Huang , Joey Shah , David Lawrence Standley
IPC分类号： H04N5/217 , H04N5/378 , H04N5/365
CPC分类号： H04N5/378 , H04N5/365
摘要： Aspects describe front-end pixel fixed pattern noise correction in imaging arrays having wide dynamic range. A photosensor of a first pixel in a first row of an array is reset and a first reset level of the first pixel is measured. The array comprises a plurality of pixels arranged in rows and columns. In response to a result of the first reset level, a reset bus is altered. A feed-forward adjustment of the photosensor of the first pixel is performed to substantially remove fixed-pattern noise. An external readout from the photosensor can occur with substantially all the fixed-pattern noise removed. In some aspects, the adjustment is performed by a switched capacitor block.
摘要翻译：方面描述了具有宽动态范围的成像阵列中的前端像素固定图案噪声校正。阵列的第一行中的第一像素的光电传感器被复位，并且测量第一像素的第一复位电平。阵列包括以行和列排列的多个像素。响应于第一复位电平的结果，复位总线被改变。执行第一像素的光传感器的前馈调整以基本上去除固定图案噪声。可以发生来自光电传感器的外部读出，其中消除了基本上所有的固定图案噪声。在一些方面，调节由开关电容器块执行。

2. 发明申请

US20130038760A1 FRONT-END PIXEL FIXED PATTERN NOISE CORRECTION IN IMAGING ARRAYS HAVING WIDE DYNAMIC RANGE 有权
标题翻译：具有宽动态范围的成像阵列中的前端像素固定图案噪声校正
公开(公告)号：US20130038760A1
公开(公告)日：2013-02-14
申请号：US13206175
申请日：2011-08-09
申请人： Laurent Blanquart , Ying Huang , Joey Shah , David Lawrence Standley
发明人： Laurent Blanquart , Ying Huang , Joey Shah , David Lawrence Standley
IPC分类号： H04N5/217 , G01J1/42
CPC分类号： H04N5/378 , H04N5/365
摘要： Aspects describe front-end pixel fixed pattern noise correction in imaging arrays having wide dynamic range. A photosensor of a first pixel in a first row of an array is reset and a first reset level of the first pixel is measured. The array comprises a plurality of pixels arranged in rows and columns. In response to a result of the first reset level, a reset bus is altered. A feed-forward adjustment of the photosensor of the first pixel is performed to substantially remove fixed-pattern noise. An external readout from the photosensor can occur with substantially all the fixed-pattern noise removed. In some aspects, the adjustment is performed by a switched capacitor block.
摘要翻译：方面描述了具有宽动态范围的成像阵列中的前端像素固定图案噪声校正。阵列的第一行中的第一像素的光电传感器被复位，并且测量第一像素的第一复位电平。阵列包括以行和列排列的多个像素。响应于第一复位电平的结果，复位总线被改变。执行第一像素的光传感器的前馈调整以基本上去除固定图案噪声。可以发生来自光电传感器的外部读出，其中消除了基本上所有的固定图案噪声。在一些方面，调节由开关电容器块执行。

3. 发明授权

US08633845B2 Low power slope-based analog-to-digital converter 有权
标题翻译：基于低功率斜率的模数转换器
公开(公告)号：US08633845B2
公开(公告)日：2014-01-21
申请号：US13409380
申请日：2012-03-01
申请人： David Lawrence Standley
发明人： David Lawrence Standley
IPC分类号： H03M1/12
CPC分类号： H03M1/002 , H03M1/164 , H03M1/56
摘要： Providing for a two-stage single-slope analog to digital converter (ADC) exhibiting high resolution in conjunction with reduced power consumption is described herein. The ADC can achieve a digital resolution of at least 13 bits according to one or more disclosed embodiments, with significantly lower power consumption than conventional high resolution analog to digital converters. In operation, bias current supplied to one or more components of the ADC can be ramped up to a high magnitude during high accuracy or high speed processes of the ADC. Upon completion of these processes, the bias current can be sharply reduced for at least a portion of a clock cycle. During a residue amplification process associated with a second stage of the ADC, bias current can be increased to a moderate level. Average power consumption can be reduced significantly, while maintaining peak power requirements.
摘要翻译：本文描述了提供结合降低的功耗的呈现高分辨率的两级单斜率模数转换器（ADC）。根据一个或多个公开的实施例，ADC可以实现至少13位的数字分辨率，具有比常规高分辨率模数转换器显着更低的功耗。在运行中，提供给ADC的一个或多个组件的偏置电流可以在ADC的高精度或高速过程期间升高到高的幅度。在完成这些处理之后，对于至少一个时钟周期的一部分，偏置电流可以急剧减小。在与ADC的第二级相关的残留放大过程中，偏置电流可以增加到中等水平。在保持峰值功率要求的同时，可以显着降低平均功耗。

4. 发明申请

US20130229293A1 LOW POWER SLOPE-BASED ANALOG-TO-DIGITAL CONVERTER 有权
标题翻译：低功率斜率模拟数字转换器
公开(公告)号：US20130229293A1
公开(公告)日：2013-09-05
申请号：US13409380
申请日：2012-03-01
申请人： David Lawrence Standley
发明人： David Lawrence Standley
IPC分类号： H03M1/12
CPC分类号： H03M1/002 , H03M1/164 , H03M1/56
摘要： Providing for a two-stage single-slope analog to digital converter (ADC) exhibiting high resolution in conjunction with reduced power consumption is described herein. The ADC can achieve a digital resolution of at least 13 bits according to one or more disclosed embodiments, with significantly lower power consumption than conventional high resolution analog to digital converters. In operation, bias current supplied to one or more components of the ADC can be ramped up to a high magnitude during high accuracy or high speed processes of the ADC. Upon completion of these processes, the bias current can be sharply reduced for at least a portion of a clock cycle. During a residue amplification process associated with a second stage of the ADC, bias current can be increased to a moderate level. Average power consumption can be reduced significantly, while maintaining peak power requirements.
摘要翻译：本文描述了提供结合降低的功耗的呈现高分辨率的两级单斜率模数转换器（ADC）。根据一个或多个公开的实施例，ADC可以实现至少13位的数字分辨率，具有比常规高分辨率模数转换器显着更低的功耗。在运行中，提供给ADC的一个或多个组件的偏置电流可以在ADC的高精度或高速过程期间升高到高的幅度。在完成这些处理之后，对于至少一个时钟周期的一部分，偏置电流可以急剧减小。在与ADC的第二级相关的残留放大过程中，偏置电流可以增加到中等水平。在保持峰值功率要求的同时，可以显着降低平均功耗。

5. 发明授权

US08436674B1 Self-scaled voltage booster 有权
公开(公告)号：US08436674B1
公开(公告)日：2013-05-07
申请号：US13428396
申请日：2012-03-23
申请人： David Lawrence Standley , Gaurang Natverbhai Patel
发明人： David Lawrence Standley , Gaurang Natverbhai Patel
IPC分类号： G11C5/14
CPC分类号： H04N5/357 , G11C5/145
摘要： Various technologies described herein pertain to automatically adjusting the strength of a voltage booster of an image sensor. A self-scaled voltage booster includes a regulator, a controller, and two or more charge pumps that can be selectively enabled and disabled by the controller. The controller generates controller signals for the charge pumps based on a duty cycle of a regulator signal generated by the regulator. Moreover, the controller can maintain the controller signals without modification for at least a predetermined minimum period of time after a prior modification of at least one of the controller signals. Further, the controller can include a duty cycle and delay module (or a plurality of duty cycle and delay modules) that detects the duty cycle of the regulator signal and maintains the controller signals without modification for at least the predetermined minimum period of time.

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