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1. 发明授权

US08583170B2 Multi-band aggregated spectrum receiver employing frequency source reuse 有权
标题翻译：采用频率源重用的多频段聚合频谱接收机
公开(公告)号：US08583170B2
公开(公告)日：2013-11-12
申请号：US12611749
申请日：2009-11-03
申请人： Lars Sundström , Stefan Andersson , Roland Strandberg
发明人： Lars Sundström , Stefan Andersson , Roland Strandberg
IPC分类号： H04M1/00 , H04B1/16 , H04B1/10
CPC分类号： H04B1/0082
摘要： Efficient carrier aggregation is enabled in a receiver employing a single frequency source, and dividing the frequency source by different frequency dividing factors to generate two or more RF LO frequencies. Received signals are down-converted to intermediate frequencies by mixing with the respective RF LO frequencies. By utilizing only a single high frequency source, embodiments of the present invention avoid spurious and injection locking issues that arise when integrating two or more frequency sources, and additionally reduce power consumption as compared to a multiple frequency source solution.
摘要翻译：在采用单个频率源的接收机中启用有效的载波聚合，并且通过不同的分频因子来划分频率源以产生两个或更多个RF LO频率。接收的信号通过与相应的RF LO频率混合而被下变频到中频。通过仅利用单个高频源，本发明的实施例避免了在集成两个或多个频率源时产生的杂散和注入锁定问题，并且与多频率源解决方案相比，另外降低功耗。

2. 发明申请

US20130155748A1 Conversion Circuit 有权
标题翻译：转换电路
公开(公告)号：US20130155748A1
公开(公告)日：2013-06-20
申请号：US13702768
申请日：2011-06-13
申请人： Lars Sundström , Roland Strandberg
发明人： Lars Sundström , Roland Strandberg
IPC分类号： H02M5/02
CPC分类号： H04B1/16 , H02M5/02 , H03D3/007 , H03D7/1466 , H03D7/1483 , H03D7/1491 , H03D2200/0086 , H03M1/002 , H03M1/12 , H04B1/0032 , H04B1/30
摘要： A conversion circuit (20) for converting a complex analog input signal having an in-phase, I, component and a quadrature-phase, Q, component resulting from frequency down conversion of a radio-frequency, RF, signal (XRF) to a frequency band covering 0 Hz into a digital representation is disclosed. It comprises a channel-selection filter unit (40) arranged to filter the complex analog input signal, thereby generating a channel-filtered I and Q components, and one or more processing units (53, 53a-b). Each processing unit comprises four mixers (60-75) for generating a first and a second frequency-translated I component and a first and a second channel-filtered Q component based on two LO signals with equal LO frequency and a 90° mutual phase shift. Furthermore, each processing unit comprises a combiner unit (85, 120) for generating a first, a second, a third, and a fourth combined signal proportional to sums and differences between said frequency translated I and Q components. The first and the fourth combined signals form a first complex signal, and the second and the third combined signals form a second complex signal. Each processing unit further comprises four ADCs (110a-d, 115a-d) for providing digital representations of the first complex signal and the second complex signal for forming said digital representation of the analog complex input signal. A related radio receiver circuit and a related electronic apparatus are also disclosed.
摘要翻译：一种转换电路（20），用于将具有由射频RF信号（XRF）的下变频产生的同相，I分量和正交相位Q分量的复数模拟输入信号转换成公开了覆盖0Hz的数字表示的频带。它包括一个频道选择滤波器单元（40），用于对复合模拟输入信号进行滤波，从而产生一个通道滤波的I和Q分量，以及一个或多个处理单元（53,53a-b）。每个处理单元包括四个混频器（60-75），用于基于具有相同的LO频率和90°相移的两个LO信号产生第一和第二频率转换的I分量和第一和第二通道滤波的Q分量。此外，每个处理单元包括用于产生与所述频率转换的I和Q分量之间的和和差成比例的第一，第二，第三和第四组合信号的组合器单元（85,120）。第一和第四组合信号形成第一复信号，第二和第三组合信号形成第二复信号。每个处理单元还包括用于提供第一复数信号和第二复信号的数字表示的四个ADC（110a-d，115a-d），用于形成模拟复合输入信号的所述数字表示。还公开了相关的无线电接收机电路和相关的电子设备。

3. 发明申请

US20100210272A1 Multi-Band Aggregated Spectrum Receiver Employing Frequency Source Reuse 有权
标题翻译：采用频率源复用的多频段聚合频谱接收机
公开(公告)号：US20100210272A1
公开(公告)日：2010-08-19
申请号：US12611749
申请日：2009-11-03
申请人： Lars Sundström , Stefan Andersson , Roland Strandberg
发明人： Lars Sundström , Stefan Andersson , Roland Strandberg
IPC分类号： H04W72/00
CPC分类号： H04B1/0082
摘要： Efficient carrier aggregation is enabled in a receiver employing a single frequency source, and dividing the frequency source by different frequency dividing factors to generate two or more RF LO frequencies. Received signals are down-converted to intermediate frequencies by mixing with the respective RF LO frequencies. By utilizing only a single high frequency source, embodiments of the present invention avoid spurious and injection locking issues that arise when integrating two or more frequency sources, and additionally reduce power consumption as compared to a multiple frequency source solution.
摘要翻译：在采用单个频率源的接收机中启用有效的载波聚合，并且通过不同的分频因子来划分频率源以产生两个或更多个RF LO频率。接收的信号通过与相应的RF LO频率混合而被下变频到中频。通过仅利用单个高频源，本发明的实施例避免了在集成两个或多个频率源时产生的杂散和注入锁定问题，并且与多频率源解决方案相比，另外降低功耗。

4. 发明授权

US08664999B2 Mixer arrangement 有权
标题翻译：搅拌机布置
公开(公告)号：US08664999B2
公开(公告)日：2014-03-04
申请号：US13514070
申请日：2010-12-07
申请人： Imad ud Din , Roland Strandberg , Lars Sundstrom
发明人： Imad ud Din , Roland Strandberg , Lars Sundstrom
IPC分类号： H04B1/26
CPC分类号： H03D7/165 , H03D7/1441 , H03D7/1458 , H03D7/1483 , H03D2200/006
摘要： A mixer arrangement for generating an analog output signal by mixing an analog input signal with a discrete-time mixing signal. The mixer arrangement comprises a plurality of unit elements. Each unit element is adapted to be in an enabled mode in a first state of an enable signal supplied to the unit element, and in a disabled mode in a second state of the enable signal. Each unit element is adapted to generate the output signal of the unit element based on the analog input signal of the mixer arrangement in the enabled mode but not in the disabled mode. The unit elements are connected for generating a common output signal as the sum of the output signals from the unit elements. The mixer arrangement is adapted to generate the analog output signal of the mixer arrangement based on the common output signal. A corresponding method is also disclosed.
摘要翻译：一种用于通过将模拟输入信号与离散时间混合信号混合来产生模拟输出信号的混频器装置。混合器装置包括多个单元元件。每个单元元件适于在提供给单元元件的使能信号的第一状态中处于使能模式，并且在使能信号的第二状态中处于禁用模式。每个单元元件适于基于混合器装置的模拟输入信号在使能模式中而不是处于禁用模式下产生单元元件的输出信号。连接单位元件以产生公共输出信号作为来自单元元件的输出信号的总和。混频器装置适于基于公共输出信号产生混频器装置的模拟输出信号。还公开了相应的方法。

5. 发明申请

US20150071391A1 Technique for Calibrating a Receiver Apparatus 有权
标题翻译：校准接收机设备的技术
公开(公告)号：US20150071391A1
公开(公告)日：2015-03-12
申请号：US14394531
申请日：2012-04-20
申请人： Leif Wilhelmsson , Roland Strandberg , Jim Svensson
发明人： Leif Wilhelmsson , Roland Strandberg , Jim Svensson
IPC分类号： H04B17/00 , H04B1/10
CPC分类号： H04B17/10 , H04B1/10 , H04L27/3863
摘要： A technique for calibrating a receiver apparatus comprising at least one analog signal processing component and an intermediate frequency, or IF, mixer for converting IF signals comprising an in-phase, or I, signal and a quadrature-phase, or Q, signal to baseband frequency signals is provided. The IF mixer is arranged downstream of the at least one analog signal processing component. A method implementation of the technique comprises the steps of determining, in a digital processing domain downstream of the IF mixer, a metric which is affected by a frequency dependency of an imbalance between I and the Q signal, or IQ-imbalance, over a signal bandwidth, generating, based on the metric thus determined, a calibration signal configured to at least partially compensate a frequency-dependency of the IQ imbalance, and feeding the calibration signal to the at least one analog signal processing component so as to calibrate the at least one analog signal processing component.
摘要翻译：一种用于校准接收机装置的技术，包括至少一个模拟信号处理部件和中频或IF混频器，用于将包括同相或I信号和正交相位或Q信号的IF信号转换成基带提供频率信号。 IF混合器布置在至少一个模拟信号处理部件的下游。该技术的方法实现包括以下步骤：在IF混合器的下游的数字处理域中，确定受信号I和Q信号之间的不平衡或IQ不平衡的频率依赖性的影响的度量带宽，基于如此确定的度量产生校准信号，所述校准信号被配置为至少部分地补偿IQ不平衡的频率依赖性，以及将所述校准信号馈送到所述至少一个模拟信号处理组件，以至少校准一个模拟信号处理组件。

6. 发明授权

US07715515B2 Method and apparatus for reducing non-montonic regions in a digitally controlled oscillator 有权
标题翻译：用于减少数字控制振荡器中的非单调区域的方法和装置
公开(公告)号：US07715515B2
公开(公告)日：2010-05-11
申请号：US11550907
申请日：2006-10-19
申请人： Thomas Olsson , Roland Strandberg , Jim Svensson
发明人： Thomas Olsson , Roland Strandberg , Jim Svensson
IPC分类号： H03D3/24
CPC分类号： H03L7/0991
摘要： The control word input to a Digitally Controlled Oscillator (DCO) is modified to reduce non-monotonic regions in the output response of the DCO. The DCO may be included in a Phase-Locked Loop (PLL) circuit for generating an output signal that locks onto either the phase or frequency of a reference signal input. By modifying the control word input to the DCO to avoid non-monotonic regions in the DCO output response, PLL phase noise is reduced. In one embodiment, the control word is modified by reordering or skipping control word values input to the DCO that correspond to non-monotonic regions in the output response of the DCO circuit.
摘要翻译：输入到数字控制振荡器（DCO）的控制字被修改以减少DCO的输出响应中的非单调区域。 DCO可以被包括在锁相环（PLL）电路中，用于产生锁定到参考信号输入的相位或频率上的输出信号。通过修改输入到DCO的控制字以避免DCO输出响应中的非单调区域，PLL相位噪声减小。在一个实施例中，通过重新排序或跳过与DCO电路的输出响应中对应于非单调区域的DCO输入的控制字值来修改控制字。

7. 发明授权

US09264156B2 Technique for calibrating a receiver apparatus 有权
标题翻译：校准接收机设备的技术
公开(公告)号：US09264156B2
公开(公告)日：2016-02-16
申请号：US14394531
申请日：2012-04-20
申请人： Leif Wilhelmsson , Roland Strandberg , Jim Svensson
发明人： Leif Wilhelmsson , Roland Strandberg , Jim Svensson
IPC分类号： H03D1/04 , H04B17/00 , H04L27/38 , H04B1/10
CPC分类号： H04B17/10 , H04B1/10 , H04L27/3863
摘要： A technique for calibrating a receiver apparatus comprising at least one analog signal processing component and an intermediate frequency, or IF, mixer for converting IF signals comprising an in-phase, or I, signal and a quadrature-phase, or Q, signal to baseband frequency signals is provided. The IF mixer is arranged downstream of the at least one analog signal processing component. A method implementation of the technique comprises the steps of determining, in a digital processing domain downstream of the IF mixer, a metric which is affected by a frequency dependency of an imbalance between I and the Q signal, or IQ-imbalance, over a signal bandwidth, generating, based on the metric thus determined, a calibration signal configured to at least partially compensate a frequency-dependency of the IQ imbalance, and feeding the calibration signal to the at least one analog signal processing component so as to calibrate the at least one analog signal processing component.
摘要翻译：一种用于校准接收机装置的技术，包括至少一个模拟信号处理部件和中频或IF混频器，用于将包括同相或I信号和正交相位或Q信号的IF信号转换成基带提供频率信号。 IF混合器布置在至少一个模拟信号处理部件的下游。该技术的方法实现包括以下步骤：在IF混合器的下游的数字处理域中，确定受信号I和Q信号之间的不平衡或IQ不平衡的频率依赖性的影响的度量带宽，基于如此确定的度量产生校准信号，所述校准信号被配置为至少部分地补偿IQ不平衡的频率依赖性，以及将所述校准信号馈送到所述至少一个模拟信号处理组件，以至少校准一个模拟信号处理组件。

8. 发明授权

US08867671B2 Conversion circuit for converting complex analog signal into digital representation 有权
标题翻译：用于将复杂模拟信号转换为数字表示的转换电路
公开(公告)号：US08867671B2
公开(公告)日：2014-10-21
申请号：US13702768
申请日：2011-06-13
申请人： Lars Sunström , Roland Strandberg
发明人： Lars Sunström , Roland Strandberg
IPC分类号： H03D3/24 , H03D7/14 , H04B1/00 , H04B1/30 , H02M5/02 , H03D3/00
CPC分类号： H04B1/16 , H02M5/02 , H03D3/007 , H03D7/1466 , H03D7/1483 , H03D7/1491 , H03D2200/0086 , H03M1/002 , H03M1/12 , H04B1/0032 , H04B1/30
摘要： A conversion circuit (20) for converting a complex analog input signal having an in-phase, I, component and a quadrature-phase, Q, component resulting from frequency down conversion of a radio-frequency, RF, signal (XRF) to a frequency band covering 0 Hz into a digital representation is disclosed. It comprises a channel-selection filter unit (40) arranged to filter the complex analog input signal, thereby generating a channel-filtered I and Q components, and one or more processing units (53, 53a-b). Each processing unit comprises four mixers (60-75) for generating a first and a second frequency-translated I component and a first and a second channel-filtered Q component based on two LO signals with equal LO frequency and a 90° mutual phase shift. Furthermore, each processing unit comprises a combiner unit (85, 120) for generating a first, a second, a third, and a fourth combined signal proportional to sums and differences between said frequency translated I and Q components. The first and the fourth combined signals form a first complex signal, and the second and the third combined signals form a second complex signal. Each processing unit further comprises four ADCs (110a-d, 115a-d) for providing digital representations of the first complex signal and the second complex signal for forming said digital representation of the analog complex input signal. A related radio receiver circuit and a related electronic apparatus are also disclosed.
摘要翻译：一种转换电路（20），用于将具有由射频RF信号（XRF）的下变频产生的同相，I分量和正交相位Q分量的复数模拟输入信号转换成公开了覆盖0Hz的数字表示的频带。它包括一个频道选择滤波器单元（40），用于对复合模拟输入信号进行滤波，从而产生一个通道滤波的I和Q分量，以及一个或多个处理单元（53,53a-b）。每个处理单元包括四个混频器（60-75），用于基于具有相同的LO频率和90°相移的两个LO信号产生第一和第二频率转换的I分量和第一和第二通道滤波的Q分量。此外，每个处理单元包括用于产生与所述频率转换的I和Q分量之间的和和差成比例的第一，第二，第三和第四组合信号的组合器单元（85,120）。第一和第四组合信号形成第一复信号，第二和第三组合信号形成第二复信号。每个处理单元还包括用于提供第一复数信号和第二复信号的数字表示的四个ADC（110a-d，115a-d），用于形成模拟复合输入信号的所述数字表示。还公开了相关的无线电接收机电路和相关的电子设备。

9. 发明申请

US20130009688A1 MIXER ARRANGEMENT 有权
标题翻译：混合装置
公开(公告)号：US20130009688A1
公开(公告)日：2013-01-10
申请号：US13514070
申请日：2010-12-07
申请人： Imad ud Din , Roland Strandberg , Lars Sundstrom
发明人： Imad ud Din , Roland Strandberg , Lars Sundstrom
IPC分类号： G06G7/16
CPC分类号： H03D7/165 , H03D7/1441 , H03D7/1458 , H03D7/1483 , H03D2200/006
摘要： A mixer arrangement for generating an analog output signal mixing an analog input signal with a discrete-time mixing signal. The mixer arrangement comprises a plurality of unit elements. Each unit element is adapted to be in an enabled mode in a first state of an enable signal supplied to the unit element, and in a disabled mode in a second state of the enable signal. Each unit element is adapted to generate the output signal of the unit element based on the analog input signal of the mixer arrangement in the enabled mode but not in the disabled mode. The unit elements are connected for generating a common output signal as the sum of the output signals from the unit elements. The arrangement is adapted to generate the analog output signal of the mixer arrangement based on the common output signal. A corresponding method is also disclosed.
摘要翻译：一种用于产生将模拟输入信号与离散时间混合信号混合的模拟输出信号的混频器装置。混合器装置包括多个单元元件。每个单元元件适于在提供给单元元件的使能信号的第一状态中处于使能模式，并且在使能信号的第二状态中处于禁用模式。每个单元元件适于基于混合器装置的模拟输入信号在使能模式中而不是在禁用模式下产生单元元件的输出信号。连接单位元件以产生公共输出信号作为来自单元元件的输出信号的总和。该装置适于基于公共输出信号产生混频器装置的模拟输出信号。还公开了相应的方法。

10. 发明申请

US20090079487A1 Time Delay Line with Low Sensitivity to Process Variations 审中-公开
标题翻译：具有低灵敏度处理变化的延时线
公开(公告)号：US20090079487A1
公开(公告)日：2009-03-26
申请号：US11861353
申请日：2007-09-26
申请人： Torkel Arnborg , Roland Strandberg
发明人： Torkel Arnborg , Roland Strandberg
IPC分类号： H03H11/26
CPC分类号： H03K5/133 , H01L27/092 , H03K2005/00123 , H03L7/0812 , H03L7/0891 , H03L7/18 , H03L7/197
摘要： A time delay line comprises a plurality of delay elements connected in series. Each delay element comprises one or more transistors that exhibit a reverse short channel effect at channel lengths within a certain range. The transistors are configured to have a channel length in the certain range in order to reduce time delay sensitivity to process variations.
摘要翻译：时间延迟线包括串联连接的多个延迟元件。每个延迟元件包括一个或多个在一定范围内的通道长度处呈现反向短通道效应的晶体管。晶体管被配置为具有在一定范围内的通道长度，以便减少对工艺变化的时间延迟灵敏度。

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