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1. 发明授权

US5648909A Static timing verification in the presence of logically false paths 失效
标题翻译：存在逻辑错误路径的静态时序验证
公开(公告)号：US5648909A
公开(公告)日：1997-07-15
申请号：US490439
申请日：1995-06-12
申请人： Larry L. Biro , Joel J. Grodstein , Jeng-Wei Pan , Nicholas L. Rethman
发明人： Larry L. Biro , Joel J. Grodstein , Jeng-Wei Pan , Nicholas L. Rethman
IPC分类号： G06F17/50 , G06F15/00 , G06G7/48
CPC分类号： G06F17/5031
摘要： In a method for improving a circuit having a logically false path through static analysis of a software model, a computer receives information describing the false path, determines a true path alternate to the false path, and analyses the circuit model with respect to the true path.
摘要翻译：在通过软件模型的静态分析改进具有逻辑错误路径的电路的方法中，计算机接收描述假路径的信息，确定与假路径交替的真实路径，并且相对于真实路径分析电路模型。

2. 发明授权

US5546320A Method for performing integrated section-level and full-chip timing verification for custom microprocessor designs 失效
标题翻译：执行定制微处理器设计的集成部分级和全芯片定时验证的方法
公开(公告)号：US5546320A
公开(公告)日：1996-08-13
申请号：US588161
申请日：1996-01-18
申请人： Larry L. Biro , Jengwei Pan
发明人： Larry L. Biro , Jengwei Pan
IPC分类号： G06F17/50
CPC分类号： G06F17/5031
摘要： A method for performing integrated section-level and full-chip timing verification is employed for integrated circuit designs that include several section designs. A plurality of bristle timing parameters define timing relationships between the section designs. A section-level verification procedure is performed for each of the section designs to determine whether the section designs conform to predetermined intra-section timing constraints. A full-chip verification procedure is performed for the integrated circuit design to determine the bristle timing parameters and to determine whether the integrated circuit design conforms with predetermined intersection timing constraints.
摘要翻译：用于执行集成部分级和全芯片定时验证的方法用于包括若干部分设计的集成电路设计。多个刷毛定时参数定义了截面设计之间的定时关系。对于每个部分设计执行部分级验证程序，以确定部分设计是否符合预定的部分内时序约束。对集成电路设计执行全芯片验证程序以确定刷毛定时参数并确定集成电路设计是否符合预定的交叉点时序约束。

3. 发明授权

US6163864A Method for cost-effective production testing of input voltage levels of the forwarded clock interface of high performance integrated circuits 失效
标题翻译：高性能集成电路转发时钟接口输入电压电平的成本效益生产测试方法
公开(公告)号：US6163864A
公开(公告)日：2000-12-19
申请号：US95149
申请日：1998-06-10
申请人： Dilip K. Bhavsar , Larry L. Biro
发明人： Dilip K. Bhavsar , Larry L. Biro
IPC分类号： G01R31/3185 , G01R31/28
CPC分类号： G01R31/318577
摘要： A boundary scan based VIH/VIL test scheme for a clock forwarded interface of an IEEE 1149.1 Standard-compliant electronic component is provided. The Standard-compliant component has a test access port (TAP) and a forwarded clock interface including data and forwarded clock inputs for receiving signals from and sending signals to external circuitry during a test operation. Connected to each of such component's data inputs is a clocked and an unclocked input buffer. Coupled to the TAP is an instruction register for receiving Standard defined and other test instructions provided by the external circuitry at the TAP. Also coupled to the TAP is a chain of boundary scan cells, each associated with a different one of the input pins and connected to the output of each input buffer coupled thereto, and a TAP controller for generating control signals to capture and shift data through the boundary scan cells in response to test instructions received by the instruction register. Compliance control circuitry, responsive to the instruction register and the TAP controller, operates to couple each BSR cell to the second input buffer when the instruction register has been loaded with a Standard defined instruction. When the instruction register has been loaded with an instruction corresponding to an input threshold voltage test of the data input pins, the compliance control circuitry couples the BSR cell to the first input buffer.
摘要翻译：提供了符合IEEE 1149.1标准的电子元件的时钟转发接口的基于边界扫描的VIH / VIL测试方案。标准兼容组件具有测试访问端口（TAP）和转发的时钟接口，包括数据和转发的时钟输入，用于在测试操作期间从外部电路接收信号和向外部电路发送信号。连接到每个这样的组件的数据输入是时钟和非锁定的输入缓冲器。连接到TAP是用于接收TAP外部电路提供的标准定义和其他测试指令的指令寄存器。还耦合到TAP的是一连串的边界扫描单元，每一个都与不同的一个输入引脚相关联，并连接到与其耦合的每个输入缓冲器的输出端，以及一个TAP控制器，用于产生控制信号以捕捉和移动数据边界扫描单元响应由指令寄存器接收到的测试指令。响应于指令寄存器和TAP控制器的符合性控制电路操作以在指令寄存器已经被加载了标准定义的指令时将每个BSR单元耦合到第二输入缓冲器。当指令寄存器已经加载了与数据输入引脚的输入阈值电压测试相对应的指令时，顺应性控制电路将BSR单元耦合到第一输入缓冲器。

4. 发明授权

US5471591A Combined write-operand queue and read-after-write dependency scoreboard 失效
标题翻译：组合写操作数队列和读写依赖记分板
公开(公告)号：US5471591A
公开(公告)日：1995-11-28
申请号：US969126
申请日：1992-10-30
申请人： John H. Edmondson , Larry L. Biro
发明人： John H. Edmondson , Larry L. Biro
IPC分类号： F02B75/02 , G06F9/38 , G06F12/08 , G06F9/312
CPC分类号： G06F12/0804 , G06F12/0811 , G06F12/0831 , G06F9/3836 , G06F9/3838 , G06F9/3857 , F02B2075/025
摘要： In a pipelined digital computer, an instruction decoder decodes register specifiers from multiple instructions, and stores them in a source queue and a destination queue. An execution unit successively obtains source specifiers of an instruction from the source queue, initiates an operation upon the source specifiers, reads a destination specifier from the destination queue, and retires the result at the specified destination. Read-after-write conflicts may occur because the execution unit may overlap execution of a plurality of instructions. Just prior to beginning execution of a current instruction, the destination queue is checked for conflict between the source specifiers of the current instruction and the destination specifiers of previously issued but not yet retired instructions. When an instruction is issued for execution, its destination specifiers in the destination queue are marked to indicate that they are associated with an executed but not yet retired instruction. In a preferred construction, each entry of the queue has a "write pending" bit that is cleared during a flush and when a read pointer is incremented. An issue pointer identifies the entry of an instruction next to be issued, so that the write-pending bit is set when the issue pointer is incremented. Each entry has two comparators enabled by the write-pending bit to detect a conflict with two source specifiers.
摘要翻译：在流水线数字计算机中，指令解码器从多个指令解码寄存器说明符，并将它们存储在源队列和目的地队列中。执行单元从源队列连续获得指令的源说明符，发起对源说明符的操作，从目的地队列读取目的地说明符，并在指定的目的地退出结果。可能发生写后冲突，因为执行单元可能与多个指令的执行重叠。在开始执行当前指令之前，检查目的地队列在当前指令的源说明符与先前发布但尚未退出的指令的目标说明符之间的冲突。当执行指令时，目标队列中的目标说明符被标记为指示它们与被执行但尚未退出的指令相关联。在优选的结构中，队列的每个条目具有在刷新期间和读取指针递增时被清除的“写入挂起”位。一个问题指针标识下一个要发出的指令的条目，以便当发出指针递增时，写入挂起位置1。每个条目都有两个比较器由写入挂起位使能，以检测与两个源说明符的冲突。

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