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1. 发明授权

US08108619B2 Cache management for partial cache line operations 有权
标题翻译：部分缓存行操作的缓存管理
公开(公告)号：US08108619B2
公开(公告)日：2012-01-31
申请号：US12024447
申请日：2008-02-01
申请人： Lakshminarayana B. Arimilli , Ravi K. Arimilli , Jerry D. Lewis , Warren E. Maule
发明人： Lakshminarayana B. Arimilli , Ravi K. Arimilli , Jerry D. Lewis , Warren E. Maule
IPC分类号： G06F12/08
CPC分类号： G06F12/0815 , G06F12/0831 , G06F12/0837 , G06F12/0886
摘要： A method of data processing in a cache memory includes caching a plurality of cache lines of data in a corresponding plurality of entries in a cache array, where each of the plurality of cache lines includes multiple data granules. For each of the plurality of cache entries, a plurality of line coherency state fields indicates an associated coherency state applicable to two or more data granules. For at least a particular cache line among the plurality of cache lines, a granule coherency state field indicates a coherency state for a particular granule of the multiple data granules in the particular cache line, where the coherency state field indicated by the granule coherency state field differs from that indicated for the particular cache line by its line coherency state field.
摘要翻译：高速缓冲存储器中的数据处理方法包括：高速缓存阵列中的相应多个条目中的多条高速缓存行数据缓存，其中多个高速缓存行中的每一条包括多个数据粒子。对于多个高速缓存条目中的每一个，多个行相关性状态字段指示适用于两个或更多个数据粒子的相关联的一致性状态。对于多个高速缓存行中的至少一个特定高速缓存行，颗粒一致性状态字段指示特定高速缓存行中的多个数据颗粒的特定颗粒的一致性状态，其中由颗粒一致性状态字段指示的一致性状态字段与特定高速缓存行通过其行一致性状态字段指示的不同。

2. 发明申请

US20090198914A1 DATA PROCESSING SYSTEM, PROCESSOR AND METHOD IN WHICH AN INTERCONNECT OPERATION INDICATES ACCEPTABILITY OF PARTIAL DATA DELIVERY 有权
标题翻译：数据处理系统，互连操作的处理器和方法显示部分数据传送的接受性
公开(公告)号：US20090198914A1
公开(公告)日：2009-08-06
申请号：US12024467
申请日：2008-02-01
申请人： LAKSHMINARAYANA B. ARIMILLI , Ravi K. Arimilli , Jerry D. Lewis , Warren E. Maule
发明人： LAKSHMINARAYANA B. ARIMILLI , Ravi K. Arimilli , Jerry D. Lewis , Warren E. Maule
IPC分类号： G06F12/00
CPC分类号： G06F12/0831 , G06F12/0886 , G06F2212/1016
摘要： According to at least one embodiment, a method of data processing in a multiprocessor data processing system includes a requesting processing unit initiating an interconnect operation including a memory access request that indicates an acceptability of a variable amount of data to service the interconnect request for data. In response to snooping the memory access request on an interconnect, a snooper selects an amount of data to supply to the requesting processing unit and transmits the selected amount of data to the requesting processing unit. The requesting processing unit receives the selected amount of data and utilizes at least some of the selected amount of data to service a processor request.
摘要翻译：根据至少一个实施例，多处理器数据处理系统中的数据处理方法包括请求处理单元发起包括存储器访问请求的互连操作，所述存储器访问请求指示可变数量的数据的可接受性来维护数据的互连请求。响应于在互连上窥探存储器访问请求，窥探者选择要提供给请求处理单元的数据量，并将所选择的数据量发送到请求处理单元。请求处理单元接收所选择的数据量并利用所选择的数量的数据中的至少一些来处理处理器请求。

3. 发明授权

US08024527B2 Partial cache line accesses based on memory access patterns 有权
标题翻译：基于内存访问模式的部分缓存行访问
公开(公告)号：US08024527B2
公开(公告)日：2011-09-20
申请号：US12024432
申请日：2008-02-01
申请人： Lakshminarayana B. Arimilli , Ravi K. Arimilli , Jerry D. Lewis , Warren E. Maule
发明人： Lakshminarayana B. Arimilli , Ravi K. Arimilli , Jerry D. Lewis , Warren E. Maule
IPC分类号： G06F12/04
CPC分类号： G06F9/30043 , G06F9/383 , G06F12/0811 , G06F12/0831 , G06F12/0886
摘要： According to a method of data processing in a multiprocessor data processing system, in response to a processor request to read a target granule of a target cache line of data containing multiple granules, a processing unit originates on an interconnect of the multiprocessor data processing system a partial read request that requests permission to read only the target granule of the target cache line. In response to a combined response to the partial read request indicating success, the combined response representing a system-wide response to the partial read request, the processing unit receives the target granule of the target cache line, supplies the target granule to a requesting processor core, and updates a coherency state of the target granule while retaining a coherency state of at least one other granule of the target cache line.
摘要翻译：根据多处理器数据处理系统中的数据处理方法，响应于读取包含多个粒度的目标高速缓存行数据的目标颗粒的处理器请求，处理单元来源于多处理器数据处理系统a的互连部分读取请求，请求权限只读取目标缓存行的目标颗粒。响应于表示成功的部分读取请求的组合响应，表示对部分读取请求的系统范围响应的组合响应，处理单元接收目标高速缓存行的目标颗粒，将目标颗粒提供给请求处理器并且在保持目标高速缓存行的至少一个其他粒子的一致性状态的同时更新目标粒子的相关性状态。

4. 发明授权

US08255635B2 Claiming coherency ownership of a partial cache line of data 有权
标题翻译：声称部分高速缓存行数据的一致性所有权
公开(公告)号：US08255635B2
公开(公告)日：2012-08-28
申请号：US12024392
申请日：2008-02-01
申请人： Lakshminarayana B. Arimilli , Ravi K. Arimilli , Jerry D. Lewis , Warren E. Maule
发明人： Lakshminarayana B. Arimilli , Ravi K. Arimilli , Jerry D. Lewis , Warren E. Maule
IPC分类号： G06F12/04
CPC分类号： G06F12/0831
摘要： According to method of data processing in a multiprocessor data processing system, in response to a processor request to modify a target granule of a target cache line of data containing multiple granules, a processing unit originates on an interconnect of the multiprocessor data processing system a data-claim-partial request that requests permission to promote only the target granule of the target cache line to a unique copy with an intent to modify the target granule. In response to a combined response to the data-claim-partial request indicating success (the combined response representing a system-wide response to the data-claim-partial-request), the processing unit promotes only the target granule of the target cache line to a unique copy by updating a coherency state of the target granule and retaining a coherency state of at least one other granule of the target cache line.
摘要翻译：根据多处理器数据处理系统中的数据处理方法，响应于修改目标高速缓存行数据包含多个粒子的处理器请求，处理单元在多处理器数据处理系统的互连上产生数据 - 要求 - 部分请求，请求仅将目标缓存行的目标颗粒推广到具有修改目标颗粒的唯一副本的权限。响应于表示成功的数据声明部分请求的组合响应（表示对数据声明部分请求的系统范围响应的组合响应），处理单元仅促进目标高速缓存行的目标颗粒通过更新目标颗粒的相关性状态并保持目标高速缓存行的至少一个其他颗粒的一致性状态来发送到唯一的副本。

5. 发明授权

US08117401B2 Interconnect operation indicating acceptability of partial data delivery 有权
标题翻译：互连操作指示部分数据传送的可接受性
公开(公告)号：US08117401B2
公开(公告)日：2012-02-14
申请号：US12024467
申请日：2008-02-01
申请人： Lakshminarayana B. Arimilli , Ravi K. Arimilli , Jerry D. Lewis , Warren E. Maule
发明人： Lakshminarayana B. Arimilli , Ravi K. Arimilli , Jerry D. Lewis , Warren E. Maule
IPC分类号： G06F12/08
CPC分类号： G06F12/0831 , G06F12/0886 , G06F2212/1016
摘要： According to at least one embodiment, a method of data processing in a multiprocessor data processing system includes a requesting processing unit initiating an interconnect operation including a memory access request that indicates an acceptability of a variable amount of data to service the interconnect request for data. In response to snooping the memory access request on an interconnect, a snooper selects an amount of data to supply to the requesting processing unit and transmits the selected amount of data to the requesting processing unit. The requesting processing unit receives the selected amount of data and utilizes at least some of the selected amount of data to service a processor request.
摘要翻译：根据至少一个实施例，多处理器数据处理系统中的数据处理方法包括请求处理单元发起包括存储器访问请求的互连操作，所述存储器访问请求指示可变数量的数据的可接受性来维护数据的互连请求。响应于在互连上窥探存储器访问请求，窥探者选择要提供给请求处理单元的数据量，并将所选择的数据量发送到请求处理单元。请求处理单元接收所选择的数据量并利用所选择的数量的数据中的至少一些来处理处理器请求。

6. 发明授权

US07958309B2 Dynamic selection of a memory access size 有权
标题翻译：动态选择内存访问大小
公开(公告)号：US07958309B2
公开(公告)日：2011-06-07
申请号：US12024476
申请日：2008-02-01
申请人： Lakshminarayana B. Arimilli , Ravi K. Arimilli , Jerry D. Lewis , Warren E. Maule
发明人： Lakshminarayana B. Arimilli , Ravi K. Arimilli , Jerry D. Lewis , Warren E. Maule
IPC分类号： G06F12/04
CPC分类号： G06F12/0886 , G06F12/0831 , G06F2212/1016 , G06F2212/502
摘要： A method of data processing in a processing unit supported by a memory hierarchy includes the processing unit performing a plurality of memory accesses to the memory hierarchy. The plurality of memory accesses includes one or more memory accesses targeting a full cache line of data. The processing unit monitors utilization of data accessed by the plurality of memory accesses, and based upon the utilization of the data, dynamically alters a memory access mode of operation so that a subsequent storage-modifying memory access targets less than a full cache line of data.
摘要翻译：由存储器层级支持的处理单元中的数据处理方法包括执行对存储器层次的多个存储器访问的处理单元。多个存储器访问包括针对全缓存数据行的一个或多个存储器访问。处理单元监视由多个存储器访问访问的数据的利用，并且基于数据的利用，动态地改变存储器访问操作模式，使得后续存储修改存储器访问目标小于完整高速缓存行数据。

7. 发明申请

US20090198915A1 DATA PROCESSING SYSTEM, PROCESSOR AND METHOD THAT DYNAMICALLY SELECT A MEMORY ACCESS SIZE 有权
标题翻译：数据处理系统，处理器和动态地选择存储器访问大小的方法
公开(公告)号：US20090198915A1
公开(公告)日：2009-08-06
申请号：US12024476
申请日：2008-02-01
申请人： LAKSHMINARAYANA B. ARIMILLI , Ravi K. Arimilli , Jerry D. Lewis , Warren E. Maule
发明人： LAKSHMINARAYANA B. ARIMILLI , Ravi K. Arimilli , Jerry D. Lewis , Warren E. Maule
IPC分类号： G06F12/08
CPC分类号： G06F12/0886 , G06F12/0831 , G06F2212/1016 , G06F2212/502
摘要： A method of data processing in a processing unit supported by a memory hierarchy includes the processing unit performing a plurality of memory accesses to the memory hierarchy. The plurality of memory accesses includes one or more memory accesses targeting a full cache line of data. The processing unit monitors utilization of data accessed by the plurality of memory accesses, and based upon the utilization of the data, dynamically alters a memory access mode of operation so that a subsequent storage-modifying memory access targets less than a full cache line of data.
摘要翻译：由存储器层级支持的处理单元中的数据处理方法包括执行对存储器层次的多个存储器访问的处理单元。多个存储器访问包括针对全缓存数据行的一个或多个存储器访问。处理单元监视由多个存储器访问访问的数据的利用，并且基于数据的利用，动态地改变存储器访问操作模式，使得后续存储修改存储器访问目标小于完整高速缓存行数据。

8. 发明申请

US20090198912A1 DATA PROCESSING SYSTEM, PROCESSOR AND METHOD FOR IMPLEMENTING CACHE MANAGEMENT FOR PARTIAL CACHE LINE OPERATIONS 有权
标题翻译：数据处理系统，用于执行部分缓存线路操作的高速缓存管理的处理器和方法
公开(公告)号：US20090198912A1
公开(公告)日：2009-08-06
申请号：US12024447
申请日：2008-02-01
申请人： LAKSHMINARAYANA B. ARIMILLI , Ravi K. Arimilli , Jerry D. Lewis , Warren E. Maule
发明人： LAKSHMINARAYANA B. ARIMILLI , Ravi K. Arimilli , Jerry D. Lewis , Warren E. Maule
IPC分类号： G06F12/00
CPC分类号： G06F12/0815 , G06F12/0831 , G06F12/0837 , G06F12/0886
摘要： A method of data processing in a cache memory includes caching a plurality of cache lines of data in a corresponding plurality of entries in a cache array, where each of the plurality of cache lines includes multiple data granules. For each of the plurality of cache entries, a plurality of line coherency state fields indicates an associated coherency state applicable to two or more data granules. For at least a particular cache line among the plurality of cache lines, a granule coherency state field indicates a coherency state for a particular granule of the multiple data granules in the particular cache line, where the coherency state field indicated by the granule coherency state field differs from that indicated for the particular cache line by its line coherency state field.
摘要翻译：高速缓冲存储器中的数据处理方法包括：高速缓存阵列中的相应多个条目中的多条高速缓存行数据缓存，其中多个高速缓存行中的每一条包括多个数据粒子。对于多个高速缓存条目中的每一个，多个行相关性状态字段指示适用于两个或更多个数据粒子的相关联的一致性状态。对于多个高速缓存行中的至少一个特定高速缓存行，颗粒一致性状态字段指示特定高速缓存行中的多个数据颗粒的特定颗粒的一致性状态，其中由颗粒一致性状态字段指示的一致性状态字段与特定高速缓存行通过其行一致性状态字段指示的不同。

9. 发明授权

US07770077B2 Using cache that is embedded in a memory hub to replace failed memory cells in a memory subsystem 有权
标题翻译：使用嵌入在内存集线器中的缓存来替换内存子系统中的故障内存单元
公开(公告)号：US07770077B2
公开(公告)日：2010-08-03
申请号：US12019141
申请日：2008-01-24
申请人： Ravi K. Arimilli , Kevin C. Gower , Warren E. Maule
发明人： Ravi K. Arimilli , Kevin C. Gower , Warren E. Maule
IPC分类号： G11C29/00
CPC分类号： G06F12/0802 , G06F11/1666 , G06F11/20 , G11C5/04 , G11C29/808
摘要： A mechanism is provided for using a cache that is embedded in a memory hub device to replace failed memory cells. A memory module comprises an integrated memory hub device. The memory hub device comprises an integrated memory device data interface that communicates with a set of memory devices coupled to the memory hub device and a cache integrated in the memory hub device. The memory hub device also comprises an integrated memory hub controller that controls the data that is read or written by the memory device data interface to the cache based on a determination whether one or more memory cells within the set of memory devices has failed.
摘要翻译：提供了一种机制，用于使用嵌入在存储器集线器设备中的高速缓存来替换故障存储器单元。存储器模块包括集成存储器集线器设备。存储器集线器设备包括与耦合到存储器集线器设备的一组存储器设备和集成在存储器集线器设备中的高速缓存器通信的集成存储器设备数据接口。存储器集线器设备还包括集成存储器集线器控制器，其基于确定存储器装置集合内的一个或多个存储器单元是否已经失败来控制由存储器件数据接口读取或写入高速缓存的数据。

10. 发明申请

US20090193290A1 System and Method to Use Cache that is Embedded in a Memory Hub to Replace Failed Memory Cells in a Memory Subsystem 有权
标题翻译：使用嵌入在内存中心中的缓存来替换内存子系统中的故障内存单元的系统和方法
公开(公告)号：US20090193290A1
公开(公告)日：2009-07-30
申请号：US12019141
申请日：2008-01-24
申请人： Ravi K. Arimilli , Kevin C. Gower , Warren E. Maule
发明人： Ravi K. Arimilli , Kevin C. Gower , Warren E. Maule
IPC分类号： G06F11/20
CPC分类号： G06F12/0802 , G06F11/1666 , G06F11/20 , G11C5/04 , G11C29/808
摘要： A memory system, data processing system, and method are provided for using cache that is embedded in a memory hub device to replace failed memory cells. A memory module comprises an integrated memory hub device. The memory hub device comprises an integrated memory device data interface that communicates with a set of memory devices coupled to the memory hub device and a cache integrated in the memory hub device. The memory hub device also comprises an integrated memory hub controller that controls the data that is read or written by the memory device data interface to the cache based on a determination whether one or more memory cells within the set of memory devices has failed.
摘要翻译：提供了一种存储系统，数据处理系统和方法，用于使用嵌入在存储器集线器设备中的高速缓存来代替故障存储器单元。存储器模块包括集成存储器集线器设备。存储器集线器设备包括与耦合到存储器集线器设备的一组存储器设备和集成在存储器集线器设备中的高速缓存器通信的集成存储器设备数据接口。存储器集线器设备还包括集成存储器集线器控制器，其基于确定存储器装置集合内的一个或多个存储器单元是否已经失败来控制由存储器件数据接口读取或写入高速缓存的数据。

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