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1. 发明申请

US20090198971A1 Heterogeneous Processing Elements 有权
标题翻译：异构处理元件
公开(公告)号：US20090198971A1
公开(公告)日：2009-08-06
申请号：US12024220
申请日：2008-02-01
申请人： Lakshminarayana B. Arimilli , Ravi K. Arimilli , Guy L. Guthrie , Charles F. Marino , William J. Starke
发明人： Lakshminarayana B. Arimilli , Ravi K. Arimilli , Guy L. Guthrie , Charles F. Marino , William J. Starke
IPC分类号： G06F9/30
CPC分类号： G06F13/12
摘要： A heterogeneous processing element model is provided where I/O devices look and act like processors. In order to be treated like a processor, an I/O processing element, or other special purpose processing element, must follow some rules and have some characteristics of a processor, such as address translation, security, interrupt handling, and exception processing, for example. The heterogeneous processing element model puts special purpose processing elements on the same playing field as processors, from a programming perspective, operating system perspective, power perspective, as the processors. The operating system can get work to a security engine, for example, in the same way it does to a processor.
摘要翻译：提供异构处理元件模型，其中I / O设备看起来像处理器一样操作。为了像处理器一样处理I / O处理元件或其他专用处理元件，必须遵循一些规则并具有处理器的某些特性，例如地址转换，安全性，中断处理和异常处理，用于例。异构处理元素模型将特殊处理元素放在与处理器相同的竞争环境中，从编程角度，操作系统的角度，功率视角，作为处理器。操作系统可以使用安全引擎，例如，与处理器相同。

2. 发明授权

US08893126B2 Binding a process to a special purpose processing element having characteristics of a processor 有权
标题翻译：将过程绑定到具有处理器特征的专用处理元件
公开(公告)号：US08893126B2
公开(公告)日：2014-11-18
申请号：US12024220
申请日：2008-02-01
申请人： Lakshminarayana B. Arimilli , Ravi K. Arimilli , Guy L. Guthrie , Charles F. Marino , William J. Starke
发明人： Lakshminarayana B. Arimilli , Ravi K. Arimilli , Guy L. Guthrie , Charles F. Marino , William J. Starke
IPC分类号： G06F9/00 , G06F13/12
CPC分类号： G06F13/12
摘要： A heterogeneous processing element model is provided where I/O devices look and act like processors. In order to be treated like a processor, an I/O processing element, or other special purpose processing element, must follow some rules and have some characteristics of a processor, such as address translation, security, interrupt handling, and exception processing, for example. The heterogeneous processing element model puts special purpose processing elements on the same playing field as processors, from a programming perspective, operating system perspective, and power perspective. The operating system can get work to a security engine, for example, in the same way it does to a processor.
摘要翻译：提供异构处理元件模型，其中I / O设备看起来像处理器一样操作。为了像处理器一样处理I / O处理元件或其他专用处理元件，必须遵循一些规则并具有处理器的某些特性，例如地址转换，安全性，中断处理和异常处理，用于例。异构处理元素模型将特殊处理元素与编程角度，操作系统角度和功能视角相结合，将处理器与处理器相同。操作系统可以使用安全引擎，例如，与处理器相同。

3. 发明授权

US10235215B2 Memory lock mechanism for a multiprocessor system 有权
公开(公告)号：US10235215B2
公开(公告)日：2019-03-19
申请号：US12024169
申请日：2008-02-01
申请人： Lakshminarayana B. Arimilli , Ravi K. Arimilli , Guy L. Guthrie , William J. Starke
发明人： Lakshminarayana B. Arimilli , Ravi K. Arimilli , Guy L. Guthrie , William J. Starke
IPC分类号： G06F17/30 , G06F9/52 , G06F9/30
摘要： A memory lock mechanism within a multi-processor system is disclosed. A lock control section is initially assigned to a data block within a system memory of the multiprocessor system. In response to a request for accessing the data block by a processing unit within the multiprocessor system, a determination is made by a memory controller whether or not the lock control section of the data block has been set. If the lock control section of the data block has been set, the request for accessing the data block is denied. Otherwise, if the lock control section of the data block has not been set, the lock control section of the data block is set, and the request for accessing the data block is allowed.

4. 发明申请

US20090198933A1 Method and Apparatus for Handling Multiple Memory Requests Within a Multiprocessor System 有权
标题翻译：在多处理器系统中处理多个存储器请求的方法和装置
公开(公告)号：US20090198933A1
公开(公告)日：2009-08-06
申请号：US12024181
申请日：2008-02-01
申请人： Lakshminarayana B. Arimilli , Ravi K. Arimilli , Guy L. Guthrie , William J. Starke
发明人： Lakshminarayana B. Arimilli , Ravi K. Arimilli , Guy L. Guthrie , William J. Starke
IPC分类号： G06F12/14
CPC分类号： G06F9/526
摘要： A method for handling multiple memory requests within a multi-processor system is disclosed. A lock control section is initially assigned to a data block within a system memory. In response to a request for accessing the data block by a processing unit, a determination is made whether or not the lock control section of the data block has been set. If the lock control section has been set, another determination is made whether or not the requesting processing unit is located beyond a predetermined distance from a memory controller. If the requesting processing unit is located beyond a predetermined distance from the memory controller, the requesting processing unit is invited to perform other functions; otherwise, the number of the requesting processing unit is placed in a queue table. However, if the lock control section has not been set, the lock control section of the data block is set, and the access request is allowed.
摘要翻译：公开了一种在多处理器系统内处理多个存储器请求的方法。锁控制部分最初被分配给系统存储器内的数据块。响应于由处理单元访问数据块的请求，确定数据块的锁定控制部分是否已经被设置。如果已经设置了锁定控制部分，则另外确定请求处理单元是否位于距离存储器控制器超过预定距离的位置。如果请求处理单元位于距存储器控制器超过预定距离的位置，则请求处理单元被邀请执行其他功能; 否则，请求处理单元的号码被放置在队列表中。然而，如果锁定控制部分尚未设置，则数据块的锁定控制部分被设置，并且允许访问请求。

5. 发明授权

US08214603B2 Method and apparatus for handling multiple memory requests within a multiprocessor system 有权
标题翻译：用于在多处理器系统内处理多个存储器请求的方法和装置
公开(公告)号：US08214603B2
公开(公告)日：2012-07-03
申请号：US12024181
申请日：2008-02-01
申请人： Lakshminarayana B. Arimilli , Ravi K. Arimilli , Guy L. Guthrie , William J. Starke
发明人： Lakshminarayana B. Arimilli , Ravi K. Arimilli , Guy L. Guthrie , William J. Starke
IPC分类号： G06F12/00 , G06F13/00
CPC分类号： G06F9/526
摘要： A method for handling multiple memory requests within a multi-processor system is disclosed. A lock control section is initially assigned to a data block within a system memory. In response to a request for accessing the data block by a processing unit, a determination is made whether or not the lock control section of the data block has been set. If the lock control section has been set, another determination is made whether or not the requesting processing unit is located beyond a predetermined distance from a memory controller. If the requesting processing unit is located beyond a predetermined distance from the memory controller, the requesting processing unit is invited to perform other functions; otherwise, the number of the requesting processing unit is placed in a queue table. However, if the lock control section has not been set, the lock control section of the data block is set, and the access request is allowed.
摘要翻译：公开了一种在多处理器系统内处理多个存储器请求的方法。锁控制部分最初被分配给系统存储器内的数据块。响应于由处理单元访问数据块的请求，确定数据块的锁定控制部分是否已经被设置。如果已经设置了锁定控制部分，则另外确定请求处理单元是否位于距离存储器控制器超过预定距离的位置。如果请求处理单元位于距存储器控制器超过预定距离的位置，则请求处理单元被邀请执行其他功能; 否则，请求处理单元的号码被放置在队列表中。然而，如果锁定控制部分尚未设置，则数据块的锁定控制部分被设置，并且允许访问请求。

6. 发明申请

US20090198849A1 Memory Lock Mechanism for a Multiprocessor System 审中-公开
标题翻译：多处理器系统的内存锁机制
公开(公告)号：US20090198849A1
公开(公告)日：2009-08-06
申请号：US12024169
申请日：2008-02-01
申请人： Lakshminarayana B. Arimilli , Ravi K. Arimilli , Guy L. Guthrie , William J. Starke
发明人： Lakshminarayana B. Arimilli , Ravi K. Arimilli , Guy L. Guthrie , William J. Starke
IPC分类号： G06F12/14
CPC分类号： G06F9/526 , G06F9/3004 , G06F9/30087 , G06F17/30171 , G06F17/30362
摘要： A memory lock mechanism within a multi-processor system is disclosed. A lock control section is initially assigned to a data block within a system memory of the multiprocessor system. In response to a request for accessing the data block by a processing unit within the multiprocessor system, a determination is made by a memory controller whether or not the lock control section of the data block has been set. If the lock control section of the data block has been set, the request for accessing the data block is denied. Otherwise, if the lock control section of the data block has not been set, the lock control section of the data block is set, and the request for accessing the data block is allowed.
摘要翻译：公开了一种多处理器系统内的存储锁定机构。锁控制部分最初被分配给多处理器系统的系统存储器内的数据块。响应于由多处理器系统内的处理单元访问数据块的请求，由存储器控制器确定数据块的锁定控制部分是否已被设置。如果已经设置了数据块的锁定控制部分，则拒绝访问数据块的请求。否则，如果未设置数据块的锁定控制部分，则设置数据块的锁定控制部分，并且允许访问数据块的请求。

7. 发明申请

US20090198695A1 Method and Apparatus for Supporting Distributed Computing Within a Multiprocessor System 审中-公开
标题翻译：在多处理器系统中支持分布式计算的方法和装置
公开(公告)号：US20090198695A1
公开(公告)日：2009-08-06
申请号：US12024245
申请日：2008-02-01
申请人： Lakshminarayana B. Arimilli , Ravi K. Arimilli , Guy L. Guthrie , William J. Starke
发明人： Lakshminarayana B. Arimilli , Ravi K. Arimilli , Guy L. Guthrie , William J. Starke
IPC分类号： G06F17/30
CPC分类号： G06F9/526 , G06F9/3004 , G06F9/30087
摘要： A locking mechanism for supporting distributed computing within a multiprocessor system is disclosed. A lock control section and a stage control section are assigned to a data block within a system memory. In response to a request for accessing the data block by a processing unit, a determination is made by a memory controller whether or not the lock control section of the data block has been set. If the lock control section of the data block has been set, the access request is denied. Otherwise, if the lock control section of the data block has not been set, another determination is made whether or not a current processing stage of the requesting processing unit matches a processing stage indicated by the stage control section. If the current processing stage of the requesting processing unit does not match the processing stage indicated by the stage control section, the access request is denied; otherwise, the access request is allowed.
摘要翻译：公开了一种用于在多处理器系统内支持分布式计算的锁定机构。锁定控制部分和级控制部分被分配给系统存储器内的数据块。响应于由处理单元访问数据块的请求，由存储器控制器确定数据块的锁定控制部分是否已经被设置。如果数据块的锁定控制部分已设置，则访问请求被拒绝。否则，如果数据块的锁定控制部分未被设置，则另外确定请求处理单元的当前处理级是否与由级控制部分指示的处理级相匹配。如果请求处理单元的当前处理阶段与舞台控制部分指示的处理阶段不匹配，则拒绝该访问请求; 否则，允许访问请求。

8. 发明申请

US20090198920A1 Processing Units Within a Multiprocessor System Adapted to Support Memory Locks 审中-公开
标题翻译：适用于支持内存锁的多处理器系统中的处理单元
公开(公告)号：US20090198920A1
公开(公告)日：2009-08-06
申请号：US12024234
申请日：2008-02-01
申请人： Lakshminarayana B. Arimilli , Ravi K. Arimilli , Guy L. Guthrie , William J. Starke
发明人： Lakshminarayana B. Arimilli , Ravi K. Arimilli , Guy L. Guthrie , William J. Starke
IPC分类号： G06F12/00
CPC分类号： G06F15/16 , G06F9/3004 , G06F9/30087 , G06F9/526
摘要： A processing unit within a multiprocessor system adapted to support memory locks is disclosed. In response to a request for accessing a data block being denied when a lock control section of the data block has been set by a memory controller, a timer countdown is started within a processing unit within a multiprocessor system. The requesting processing unit can relinquish the access request once the timer countdown has reached a timeout period.
摘要翻译：公开了一种适于支持存储器锁的多处理器系统内的处理单元。响应于当由存储器控制器设置数据块的锁定控制部分时访问被拒绝的数据块的请求，在多处理器系统内的处理单元内启动定时器倒计时。一旦定时器倒计时达到超时时间，请求处理单元可以放弃访问请求。

9. 发明申请

US20090198916A1 Method and Apparatus for Supporting Low-Overhead Memory Locks Within a Multiprocessor System 审中-公开
标题翻译：用于支持多处理器系统内的低成本内存锁的方法和装置
公开(公告)号：US20090198916A1
公开(公告)日：2009-08-06
申请号：US12024223
申请日：2008-02-01
申请人： Lakshminarayana B. Arimilli , Ravi K. Arimilli , Guy L. Guthrie , Edward J. Seminaro , William J. Starke
发明人： Lakshminarayana B. Arimilli , Ravi K. Arimilli , Guy L. Guthrie , Edward J. Seminaro , William J. Starke
IPC分类号： G06F12/14
CPC分类号： G06F12/1466 , G06F9/3004 , G06F9/30087
摘要： A method for supporting low-overhead memory locks within a multi-processor system is disclosed. A lock control section is initially assigned to a data block within a system memory of the multiprocessor system. In response to a request for accessing the data block by a processing unit within the multiprocessor system, a determination is made by a memory controller whether or not the lock control section of the data block has been set. If the lock control section of the data block has been set, the request for accessing the data block is ignored. Otherwise, if the lock control section of the data block has not been set, the lock control section of the data block is set, and the request for accessing the data block is allowed.
摘要翻译：公开了一种用于支持多处理器系统内的低开销存储器锁的方法。锁控制部分最初被分配给多处理器系统的系统存储器内的数据块。响应于由多处理器系统内的处理单元访问数据块的请求，由存储器控制器确定数据块的锁定控制部分是否已被设置。如果已经设置了数据块的锁定控制部分，则忽略访问数据块的请求。否则，如果未设置数据块的锁定控制部分，则设置数据块的锁定控制部分，并且允许访问数据块的请求。

10. 发明申请

US20100257317A1 Virtual Barrier Synchronization Cache 失效
标题翻译：虚拟障碍同步缓存
公开(公告)号：US20100257317A1
公开(公告)日：2010-10-07
申请号：US12419364
申请日：2009-04-07
申请人： Ravi K. Arimilli , Guy L. Guthrie , Robert A. Cargnoni , William J. Starke , Derek E. Williams
发明人： Ravi K. Arimilli , Guy L. Guthrie , Robert A. Cargnoni , William J. Starke , Derek E. Williams
IPC分类号： G06F12/08 , G06F12/00
CPC分类号： G06F12/0811 , G06F9/522
摘要： A data processing system includes an interconnect fabric, a system memory coupled to the interconnect fabric and including a virtual barrier synchronization region allocated to storage of virtual barrier synchronization registers (VBSRs), and a plurality of processing units coupled to the interconnect fabric and operable to access the virtual barrier synchronization region of the system memory. Each of the plurality of processing units includes a processor core and a cache memory including a cache array that caches VBSR lines from the virtual barrier synchronization region of the system memory and a cache controller. The cache controller, responsive to a store request from the processor core to update a particular VBSR line, performs a non-blocking update of the cache array in each other of the plurality of processing units contemporaneously holding a copy of the particular VBSR line by transmitting a VBSR update command on the interconnect fabric.
摘要翻译：数据处理系统包括互连结构，耦合到互连结构并包括分配给虚拟屏障同步寄存器（VBSR）的存储的虚拟屏障同步区域的系统存储器，以及耦合到互连结构的多个处理单元，访问系统内存的虚拟屏障同步区域。多个处理单元中的每一个包括处理器核心和高速缓存存储器，其包括从系统存储器的虚拟屏障同步区域缓存VBSR行的缓存阵列和高速缓存控制器。高速缓存控制器响应于来自处理器核心的存储请求来更新特定VBSR线路，通过发送来同时保存特定VBSR线路的副本的多个处理单元中的彼此之间的高速缓存阵列的非阻塞更新互连结构上的VBSR更新命令。

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