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    • 4. 发明专利
    • FR2830968A1
    • 2003-04-18
    • FR0206892
    • 2002-06-05
    • LG PHILIPS LCD CO LTD
    • LEE SEOK WOOCHOI SU KYUNG
    • G02F1/133G09G3/20G09G3/36H03M1/66
    • A data driving apparatus for a liquid crystal display includes a digital-to-analog converter part for converting input pixel data into a plurality of pixel signals and time-dividing the converted pixel data signals to time-divided pixel signals, wherein the number of the converted pixel signals is greater than that of the time-divided pixel signals, at least two output buffer parts for sequentially receiving the pixel signals from the digital-to-analog converter part, buffering the time-divided pixel signals, and outputting the buffered time-divided pixel signals to a plurality of data lines, at least two of the plurality of output buffer parts being commonly connected to the digital-to-analog converter part, and a timing controller for controlling the digital-to-analog converter part and the output buffer parts and time-dividing the pixel data supplied to the digital-to-analog converter part into at least two regions to sequentially supply the time-divided pixel data to the data lines.
    • 9. 发明专利
    • FR2830968B1
    • 2004-11-19
    • FR0206892
    • 2002-06-05
    • LG PHILIPS LCD CO LTD
    • LEE SEOK WOOCHOI SU KYUNG
    • G02F1/133G09G3/20G09G3/36H03M1/66
    • A data driving apparatus for a liquid crystal display includes a digital-to-analog converter part for converting input pixel data into a plurality of pixel signals and time-dividing the converted pixel data signals to time-divided pixel signals, wherein the number of the converted pixel signals is greater than that of the time-divided pixel signals, at least two output buffer parts for sequentially receiving the pixel signals from the digital-to-analog converter part, buffering the time-divided pixel signals, and outputting the buffered time-divided pixel signals to a plurality of data lines, at least two of the plurality of output buffer parts being commonly connected to the digital-to-analog converter part, and a timing controller for controlling the digital-to-analog converter part and the output buffer parts and time-dividing the pixel data supplied to the digital-to-analog converter part into at least two regions to sequentially supply the time-divided pixel data to the data lines.