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    • 6. 发明申请
    • TEST PATTERN OF SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
    • 半导体器件的测试图及其制造方法
    • US20090166619A1
    • 2009-07-02
    • US12262005
    • 2008-10-30
    • Chan Ho PARK
    • Chan Ho PARK
    • H01L23/58H01L21/76
    • H01L22/34H01L2924/0002H01L2924/00
    • A method of manufacturing a test pattern for a semiconductor device includes the steps of forming, on a semiconductor substrate, a moat mask pattern including plural moat lines patterned in a comb-shape and etching a portion of the semiconductor substrate exposed by the moat mask pattern, to form a trench. The method further includes gap-filling the trench with an insulation material to form a field separator, planarizing the semiconductor substrate having the field separator formed thereon, and forming a poly comb pattern on the planarized semiconductor substrate. The poly comb pattern is formed such that the moat lines are arranged between lines of the poly comb pattern.
    • 制造半导体器件的测试图案的方法包括以下步骤:在半导体衬底上形成包括以梳状形成图案的多条护城河纹线的护城河掩模图案,并且蚀刻通过护城河掩模图案曝光的半导体衬底的一部分 ,形成沟槽。 该方法还包括用绝缘材料填充沟槽以形成场分离器,对其上形成有场分离器的半导体衬底进行平面化,并在平坦化半导体衬底上形成多梳状图案。 多梳形图案形成为使得护城河线布置在多梳图案的线之间。