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1. 发明授权

US07577042B2 Method of programming multi-level semiconductor memory device and multi-level semiconductor memory device 有权
标题翻译：编程多电平半导体存储器件和多电平半导体存储器件的方法
公开(公告)号：US07577042B2
公开(公告)日：2009-08-18
申请号：US11978578
申请日：2007-10-30
申请人： Jae-woong Hyun , Kyoung-lae Cho , Kyu-charn Park , Yoon-dong Park , Choong-ho Lee , Sung-jae Byun
发明人： Jae-woong Hyun , Kyoung-lae Cho , Kyu-charn Park , Yoon-dong Park , Choong-ho Lee , Sung-jae Byun
IPC分类号： G11C7/00
CPC分类号： G11C11/5628 , G11C16/10 , G11C2211/5642
摘要： Provided in one example embodiment, a method of programming n bits of data to a semiconductor memory device may include outputting a first bit of data written in a memory cell from a first latch, storing the first bit of the data to a third latch, storing a second bit of the data to the first latch, outputting the second bit of the data from the first latch, storing the second bit of the data to the second latch, and writing the second bit of the data stored in the second latch to the memory cell with reference to a data storage state of the first bit of the data stored in the third latch.
摘要翻译：在一个示例性实施例中提供了一种将半位数据数据编程到半导体存储器件的方法可以包括从第一锁存器输出写入存储器单元中的第一位数据，将第一位数据存储到第三锁存器，存储将数据的第二位输出到第一锁存器，从第一锁存器输出数据的第二位，将数据的第二位存储到第二锁存器，以及将存储在第二锁存器中的数据的第二位写入到参考存储在第三锁存器中的数据的第一位的数据存储状态的存储器单元。

2. 发明申请

US20080170434A1 Memory cell programming methods capable of reducing coupling effects 失效
标题翻译：能够减少耦合效应的存储单元编程方法
公开(公告)号：US20080170434A1
公开(公告)日：2008-07-17
申请号：US12000493
申请日：2007-12-13
申请人： Kyoung-lae Cho , Jae-woong Hyun , Sung-jae Byun , Kyu-charn Park , Yoon-dong Park , Choong-ho Lee
发明人： Kyoung-lae Cho , Jae-woong Hyun , Sung-jae Byun , Kyu-charn Park , Yoon-dong Park , Choong-ho Lee
IPC分类号： G11C16/04 , G11C16/06
CPC分类号： G11C16/0483 , G11C11/5628 , G11C2211/5648
摘要： In a memory cell programming method, first through n-th programming operations are performed to program first through n-th bits of the n bits of data using the plurality of threshold voltage distributions. The first through n-th programming operations are performed sequentially. A threshold voltage difference between threshold voltage distributions used in the n-th programming operation is less than or equal to at least one threshold voltage difference between threshold voltage distributions used in the first through (n−1)-th programming operations.
摘要翻译：在存储单元编程方法中，执行第一至第n编程操作，以使用多个阈值电压分布对n位数据的第一至第n位进行编程。顺序执行第一至第n编程操作。在第n编程操作中使用的阈值电压分布之间的阈值电压差小于或等于在第一至第（n-1）编程操作中使用的阈值电压分布之间的至少一个阈值电压差。

3. 发明授权

US07649784B2 Memory cell programming methods capable of reducing coupling effects 失效
标题翻译：能够减少耦合效应的存储单元编程方法
公开(公告)号：US07649784B2
公开(公告)日：2010-01-19
申请号：US12000493
申请日：2007-12-13
申请人： Kyoung-Iae Cho , Jae-woong Hyun , Sung-jae Byun , Kyu-charn Park , Yoon-dong Park , Choong-ho Lee
发明人： Kyoung-Iae Cho , Jae-woong Hyun , Sung-jae Byun , Kyu-charn Park , Yoon-dong Park , Choong-ho Lee
IPC分类号： G11C11/03
CPC分类号： G11C16/0483 , G11C11/5628 , G11C2211/5648
摘要： In a memory cell programming method, first through n-th programming operations are performed to program first through n-th bits of the n bits of data using the plurality of threshold voltage distributions. The first through n-th programming operations are performed sequentially. A threshold voltage difference between threshold voltage distributions used in the n-th programming operation is less than or equal to at least one threshold voltage difference between threshold voltage distributions used in the first through (n−1)-th programming operations.
摘要翻译：在存储单元编程方法中，执行第一至第n编程操作，以使用多个阈值电压分布对n位数据的第一至第n位进行编程。顺序执行第一至第n编程操作。在第n编程操作中使用的阈值电压分布之间的阈值电压差小于或等于在第一至第（n-1）编程操作中使用的阈值电压分布之间的至少一个阈值电压差。

4. 发明申请

US20080242011A1 Method of fabricating non-volatile memory device 有权
标题翻译：制造非易失性存储器件的方法
公开(公告)号：US20080242011A1
公开(公告)日：2008-10-02
申请号：US11978567
申请日：2007-10-30
申请人： Seung-hwan Song , Yoon-dong Park , June-mo Koo , Suk-pil Kim , Jae-woong Hyun , Choong-ho Lee , Tae-hun Kim
发明人： Seung-hwan Song , Yoon-dong Park , June-mo Koo , Suk-pil Kim , Jae-woong Hyun , Choong-ho Lee , Tae-hun Kim
IPC分类号： H01L21/84
CPC分类号： H01L21/84 , H01L27/105 , H01L27/1052 , H01L27/115 , H01L27/11521 , H01L27/11524 , H01L27/1203
摘要： A method of fabricating a non-volatile memory device according to example embodiments may include forming a semiconductor layer on a substrate. A plurality of lower charge storing layers may be formed on a bottom surface of the semiconductor layer. A plurality of lower control gate electrodes may be formed on the plurality of lower charge storing layers. A plurality of upper charge storing layers may be formed on a top surface of the semiconductor layer. A plurality of upper control gate electrodes may be formed on the plurality of upper charge storing layers, wherein the plurality of lower and upper control gate electrodes may be arranged alternately.
摘要翻译：根据示例性实施例的制造非易失性存储器件的方法可包括在衬底上形成半导体层。多个下电荷存储层可以形成在半导体层的底表面上。可以在多个下电荷存储层上形成多个下控制栅电极。多个上电荷存储层可以形成在半导体层的顶表面上。多个上部控制栅极电极可以形成在多个上部电荷存储层上，其中多个下部和上部控制栅电极可以交替布置。

5. 发明授权

US07585755B2 Method of fabricating non-volatile memory device 有权
标题翻译：制造非易失性存储器件的方法
公开(公告)号：US07585755B2
公开(公告)日：2009-09-08
申请号：US11978567
申请日：2007-10-30
申请人： Seung-hwan Song , Yoon-dong Park , June-mo Koo , Suk-pil Kim , Jae-woong Hyun , Choong-ho Lee , Tae-hun Kim
发明人： Seung-hwan Song , Yoon-dong Park , June-mo Koo , Suk-pil Kim , Jae-woong Hyun , Choong-ho Lee , Tae-hun Kim
IPC分类号： H01L21/8239 , H01L29/788 , H01L29/792 , H01L27/105
CPC分类号： H01L21/84 , H01L27/105 , H01L27/1052 , H01L27/115 , H01L27/11521 , H01L27/11524 , H01L27/1203
摘要： A method of fabricating a non-volatile memory device according to example embodiments may include forming a semiconductor layer on a substrate. A plurality of lower charge storing layers may be formed on a bottom surface of the semiconductor layer. A plurality of lower control gate electrodes may be formed on the plurality of lower charge storing layers. A plurality of upper charge storing layers may be formed on a top surface of the semiconductor layer. A plurality of upper control gate electrodes may be formed on the plurality of upper charge storing layers, wherein the plurality of lower and upper control gate electrodes may be arranged alternately.
摘要翻译：根据示例性实施例的制造非易失性存储器件的方法可包括在衬底上形成半导体层。多个下电荷存储层可以形成在半导体层的底表面上。可以在多个下电荷存储层上形成多个下控制栅电极。多个上电荷存储层可以形成在半导体层的顶表面上。多个上部控制栅极电极可以形成在多个上部电荷存储层上，其中多个下部和上部控制栅电极可以交替布置。

6. 发明授权

US08154065B2 Semiconductor memory devices including a vertical channel transistor having a buried bit line 有权
标题翻译：半导体存储器件包括具有埋入位线的垂直沟道晶体管
公开(公告)号：US08154065B2
公开(公告)日：2012-04-10
申请号：US12418879
申请日：2009-04-06
申请人： Jae-man Yoon , Dong-gun Park , Choong-ho Lee , Moon-suk Yi , Chul Lee
发明人： Jae-man Yoon , Dong-gun Park , Choong-ho Lee , Moon-suk Yi , Chul Lee
IPC分类号： H01L27/108
CPC分类号： H01L27/10885 , H01L27/0207 , H01L27/10814 , H01L27/10876 , H01L29/66666
摘要： Semiconductor memory devices include a semiconductor substrate and a plurality of semiconductor material pillars in a spaced relationship on the semiconductor substrate. Respective surrounding gate electrodes surround ones of the pillars. A first source/drain region is in the semiconductor substrate between adjacent ones of the pillars and a second source/drain region is in an upper portion of at least one of the adjacent pillars. A buried bit line is in the first source/drain region and electrically coupled to the first source/drain region and a storage node electrode is on the upper portion of the at least one of the adjacent pillars and electrically contacting with the second source/drain region.
摘要翻译：半导体存储器件包括在半导体衬底上具有间隔关系的半导体衬底和多个半导体材料柱。相邻的围绕电极围绕其中的一个柱。第一源极/漏极区域在相邻的柱之间的半导体衬底中，并且第二源极/漏极区域位于至少一个相邻支柱的上部。掩埋位线在第一源极/漏极区域中并且电耦合到第一源极/漏极区域，并且存储节点电极在相邻柱的至少一个的上部上并且与第二源极/漏极地区。

7. 发明授权

US08044451B2 Method of manufacturing semiconductor device having notched gate MOSFET 有权
标题翻译：具有开槽栅极MOSFET的半导体器件的制造方法
公开(公告)号：US08044451B2
公开(公告)日：2011-10-25
申请号：US12498615
申请日：2009-07-07
申请人： Byung-yong Choi , Choong-ho Lee , Dong-won Kim , Dong-gun Park
发明人： Byung-yong Choi , Choong-ho Lee , Dong-won Kim , Dong-gun Park
IPC分类号： H01L29/788
CPC分类号： H01L21/26586 , H01L29/665 , H01L29/66537 , H01L29/66553 , H01L29/6656 , H01L29/6659 , H01L29/66621 , H01L29/7833 , H01L29/7834
摘要： Provided is a method of manufacturing a semiconductor device, by which a cell transistor formed on a cell array area of a semiconductor substrate employs a structure in which an electrode in the shape of spacers is used to form a gate and a multi-bit operation is possible using localized bits, and transistors having structures optimized to satisfy different requirements depending upon functions of the transistors can be formed on a peripheral circuit area which is the residual area of the semiconductor substrate. In this method, a cell transistor is formed on the cell array area. The cell transistor includes a notch gate structure, a first channel region formed on a semiconductor substrate under the notch gate structure, a source region and a drain region formed on both sides of the first channel region, a first gate insulation film formed between the first channel region and the notch gate structure, and a memory layer locally formed on areas adjacent to the source and drain regions between the first channel region and the notch gate structure. At the same time that the cell transistor is formed, a plurality of peripheral circuit transistors including at least one transistor having a different structure from the cell transistor are formed on the peripheral circuit area.
摘要翻译：提供一种制造半导体器件的方法，通过该方法，形成在半导体衬底的单元阵列区域上的单元晶体管采用其中使用间隔物形状的电极形成栅极并且多位操作是可能使用局部位，并且可以在作为半导体衬底的剩余区域的外围电路区域上形成具有根据晶体管的功能而被优化以满足不同要求的结构的晶体管。在该方法中，在单元阵列区域上形成单元晶体管。单元晶体管包括陷波门结构，在陷波栅结构下形成在半导体衬底上的第一沟道区，形成在第一沟道区的两侧的源区和漏区，形成在第一沟道区之间的第一栅极绝缘膜沟道区域和陷波门结构，以及局部地形成在与第一沟道区和陷波栅结构之间的源极和漏极区相邻的区域上的存储层。在形成单元晶体管的同时，在外围电路区域上形成有包含至少一个具有与单元晶体管不同的结构的晶体管的多个外围电路晶体管。

8. 发明申请

US20100128522A1 Flash memory device and programming/erasing method of the same 有权
标题翻译：闪存设备和编程/擦除方法相同
公开(公告)号：US20100128522A1
公开(公告)日：2010-05-27
申请号：US12591428
申请日：2009-11-19
申请人： Dong-uk Choi , Jung-dal Choi , Choong-ho Lee , Sung-hoi Hur , Min-tai Yu
发明人： Dong-uk Choi , Jung-dal Choi , Choong-ho Lee , Sung-hoi Hur , Min-tai Yu
IPC分类号： G11C16/16 , G11C16/04 , G11C16/12
CPC分类号： G11C16/16 , G11C16/0483 , G11C16/10
摘要： A flash memory device includes a bulk region, first through nth memory cell transistors arranged in a row on the bulk region, first through nth word lines respectively connected to gates of the first through nth memory cell transistors, a first dummy cell transistor connected to the first memory cell transistor, a first dummy word line connected to a gate of the first dummy cell transistor, a first selection transistor connected to the first dummy cell transistor, a first selection line connected to a gate of the first selection transistor, and a voltage control unit connected to the first selection line, the voltage control unit being adapted to output to the first selection line a voltage lower than a voltage applied to the bulk region, in an erasing mode for erasing the first through nth memory cell transistors.
摘要翻译：闪速存储器件包括体区域，在体区域上排列成行的第一至第n个存储单元晶体管，分别连接到第一至第n存储单元晶体管的栅极的第一至第n字线，连接到第一存储单元晶体管，连接到第一虚设单元晶体管的栅极的第一虚拟字线，连接到第一虚设单元晶体管的第一选择晶体管，连接到第一选择晶体管的栅极的第一选择线，控制单元连接到第一选择线，电压控制单元适于在以擦除第一至第n个存储单元晶体管的擦除模式中向第一选择线输出低于施加到体区的电压的电压。

9. 发明授权

US07675105B2 Non-volatile memory device for 2-bit operation and method of fabricating the same 失效
标题翻译：用于2位操作的非易失性存储器件及其制造方法
公开(公告)号：US07675105B2
公开(公告)日：2010-03-09
申请号：US11376518
申请日：2006-03-15
申请人： Byung-yong Choi , Dong-gun Park , Yun-gi Kim , Choong-ho Lee , Young-mi Lee , Hye-jin Cho
发明人： Byung-yong Choi , Dong-gun Park , Yun-gi Kim , Choong-ho Lee , Young-mi Lee , Hye-jin Cho
IPC分类号： H01L27/108 , H01L29/94
CPC分类号： H01L27/11568 , H01L21/28273 , H01L21/28282 , H01L27/0207 , H01L27/115 , H01L27/11519 , H01L27/11521 , H01L29/7887 , H01L29/7923
摘要： A non-volatile memory device for 2-bit operation and a method of fabricating the same are provided. The non-volatile memory device includes an active region and a gate extending in a word line direction on a semiconductor substrate, and crossing each other repeatedly; a charge storage layer disposed below the gate, and confined at a portion where the gate and the active region cross; a charge blocking layer formed on the charge storage layer; a tunnel dielectric layer formed below the charge storage layer; first and second source/drain regions formed in the active region exposed by the gate; and first and second bit lines crossing the word line direction. The active region may be formed in a first zigzag pattern and/or the gate may be formed in a second zigzag pattern in symmetry with the first zigzag pattern.
摘要翻译：提供了一种用于2位操作的非易失性存储器件及其制造方法。非易失性存储器件包括在半导体衬底上沿着字线方向延伸的有源区和栅极，并且重复地交叉; 电荷存储层，设置在所述栅极的下方，并限制在所述栅极和所述有源区域交叉的部分; 形成在电荷存储层上的电荷阻挡层; 形成在电荷存储层下面的隧道介电层; 在由栅极暴露的有源区中形成的第一和第二源/漏区; 以及与字线方向交叉的第一和第二位线。有源区可以形成为第一之字形图案和/或栅极可以以与第一曲折图案对称的第二曲折图案形成。

10. 发明授权

US07586149B2 Circuit device including vertical transistors connected to buried bitlines and method of manufacturing the same 有权
标题翻译：电路装置包括连接到埋地位线的垂直晶体管及其制造方法
公开(公告)号：US07586149B2
公开(公告)日：2009-09-08
申请号：US11541756
申请日：2006-10-02
申请人： Jae-man Yoon , Dong-gun Park , Kang-yoon Lee , Choong-ho Lee , Bong-soo Kim , Seong-goo Kim , Hyeoung-won Seo , Seung-bae Park
发明人： Jae-man Yoon , Dong-gun Park , Kang-yoon Lee , Choong-ho Lee , Bong-soo Kim , Seong-goo Kim , Hyeoung-won Seo , Seung-bae Park
IPC分类号： H01L23/528 , H01L27/108
CPC分类号： H01L29/66666 , H01L21/823885 , H01L27/10876 , H01L27/10885 , H01L27/10894 , H01L29/7827 , H01L2924/0002 , H01L2924/00
摘要： A circuit device including vertical transistors connected to buried bitlines and a method of manufacturing the circuit device. The circuit device includes a semiconductor substrate including a peripheral circuit region and left and right cell regions at both sides of the peripheral circuit region, bottom active regions arranged on the semiconductor substrate to be spaced apart from one another in a column direction and to extend from the peripheral circuit region alternately to the left cell region and the right cell region in a row direction, channel pillars protruding from the bottom active regions in a vertical direction and arranged to be aligned in the row direction and spaced apart from one another, gate electrodes provided with a gate dielectric layer and attached to surround side surfaces of the channel pillars, and buried bitlines extending along the bottom active regions, the bottom active regions including a bottom source/drain region.
摘要翻译：一种包括连接到掩埋位线的垂直晶体管的电路器件和制造该电路器件的方法。该电路装置包括半导体衬底，该半导体衬底包括外围电路区域和在外围电路区域的两侧的左侧和右侧电池区域，布置在半导体衬底上的底部有源区域在列方向上彼此间隔开并从所述外围电路区域与所述左侧单元区域和右侧单元区域交替地排列成行方向，所述通道柱从所述底部有源区域沿垂直方向突出并且被配置为在所述行方向上彼此对准并且彼此间隔开，栅电极设置有栅介电层并且被附接到环绕通道柱的侧表面，以及沿底部有源区延伸的掩埋位线，底部有源区包括底部源极/漏极区。

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