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1. 发明授权

US07670912B2 Methods of fabricating multichannel metal oxide semiconductor (MOS) transistors 有权
标题翻译：制造多通道金属氧化物半导体（MOS）晶体管的方法
公开(公告)号：US07670912B2
公开(公告)日：2010-03-02
申请号：US10797463
申请日：2004-03-10
申请人： Kyoung-Hwan Yeo , Dong-Gun Park , Jeong-Dong Choe
发明人： Kyoung-Hwan Yeo , Dong-Gun Park , Jeong-Dong Choe
IPC分类号： H01L21/336
CPC分类号： H01L29/66484 , H01L21/8221 , H01L21/823412 , H01L27/0688 , H01L29/7831
摘要： Unit cells of metal oxide semiconductor (MOS) transistors are provided including an integrated circuit substrate an a MOS transistor on the integrated circuit substrate. The MOS transistor includes a source region, a drain region and a gate. The gate is positioned between the source region and the drain region. A horizontal channel is provided between the source and drain regions. The horizontal channel includes at least two spaced apart horizontal channel regions. Related methods of fabricating MOS transistors are also provided.
摘要翻译：提供金属氧化物半导体（MOS）晶体管的单元电池，其包括集成电路基板和集成电路基板上的MOS晶体管。 MOS晶体管包括源极区，漏极区和栅极。栅极位于源极区域和漏极区域之间。在源区和漏区之间提供水平通道。水平通道包括至少两个间隔开的水平通道区域。还提供了制造MOS晶体管的相关方法。

2. 发明授权

US07321144B2 Semiconductor device employing buried insulating layer and method of fabricating the same 有权
标题翻译：采用埋层绝缘层的半导体器件及其制造方法
公开(公告)号：US07321144B2
公开(公告)日：2008-01-22
申请号：US11011258
申请日：2004-12-13
申请人： Chang-Woo Oh , Dong-Gun Park , Jeong-Dong Choe , Kyoung-Hwan Yeo
发明人： Chang-Woo Oh , Dong-Gun Park , Jeong-Dong Choe , Kyoung-Hwan Yeo
IPC分类号： H01L27/108 , H01L29/76 , H01L29/94 , H01L31/119
CPC分类号： H01L29/66651 , H01L27/10873 , H01L29/0653 , H01L29/66659
摘要： A semiconductor device employs an asymmetrical buried insulating layer, and a method of fabricating the same. The semiconductor device includes a lower semiconductor substrate. An upper silicon pattern is located on the lower semiconductor substrate. The upper silicon pattern includes a channel region, and a source region and a drain region spaced apart from each other by the channel region. A gate electrode is electrically insulated from the upper silicon pattern and intersects over the channel region. A bit line and a cell capacitor are electrically connected to the source region and the drain region, respectively. A buried insulating layer is interposed between the drain region and the lower semiconductor substrate. The buried insulating layer has an extension portion partially interposed between the channel region and the lower semiconductor substrate.
摘要翻译：半导体器件采用非对称埋层绝缘层及其制造方法。半导体器件包括下半导体衬底。上硅图案位于下半导体衬底上。上部硅图案包括通道区域以及由沟道区域彼此间隔开的源极区域和漏极区域。栅电极与上硅图案电绝缘，并且在沟道区域上相交。位线和单元电容器分别电连接到源极区域和漏极区域。掩埋绝缘层插入在漏区和下半导体衬底之间。掩埋绝缘层具有部分插入在沟道区域和下半导体衬底之间的延伸部分。

3. 发明申请

US20050133881A1 Semiconductor device employing buried insulating layer and method of fabricating the same 有权
标题翻译：采用埋层绝缘层的半导体器件及其制造方法
公开(公告)号：US20050133881A1
公开(公告)日：2005-06-23
申请号：US11011258
申请日：2004-12-13
申请人： Chang-Woo Oh , Dong-Gun Park , Jeong-Dong Choe , Kyoung-Hwan Yeo
发明人： Chang-Woo Oh , Dong-Gun Park , Jeong-Dong Choe , Kyoung-Hwan Yeo
IPC分类号： H01L27/108 , H01L21/336 , H01L21/8238 , H01L21/8242 , H01L29/00 , H01L29/06
CPC分类号： H01L29/66651 , H01L27/10873 , H01L29/0653 , H01L29/66659
摘要： A semiconductor device employs an asymmetrical buried insulating layer, and a method of fabricating the same. The semiconductor device includes a lower semiconductor substrate. An upper silicon pattern is located on the lower semiconductor substrate. The upper silicon pattern includes a channel region, and a source region and a drain region spaced apart from each other by the channel region. A gate electrode is electrically insulated from the upper silicon pattern and intersects over the channel region. A bit line and a cell capacitor are electrically connected to the source region and the drain region, respectively. A buried insulating layer is interposed between the drain region and the lower semiconductor substrate. The buried insulating layer has an extension portion partially interposed between the channel region and the lower semiconductor substrate.
摘要翻译：半导体器件采用非对称埋层绝缘层及其制造方法。半导体器件包括下半导体衬底。上硅图案位于下半导体衬底上。上部硅图案包括通道区域以及由沟道区域彼此间隔开的源极区域和漏极区域。栅电极与上硅图案电绝缘，并且在沟道区域上相交。位线和单元电容器分别电连接到源极区域和漏极区域。掩埋绝缘层插入在漏区和下半导体衬底之间。掩埋绝缘层具有部分插入在沟道区域和下半导体衬底之间的延伸部分。

4. 发明授权

US07575964B2 Semiconductor device employing buried insulating layer and method of fabricating the same 失效
标题翻译：采用埋层绝缘层的半导体器件及其制造方法
公开(公告)号：US07575964B2
公开(公告)日：2009-08-18
申请号：US11944260
申请日：2007-11-21
申请人： Chang-Woo Oh , Dong-Gun Park , Jeong-Dong Choe , Kyoung-Hwan Yeo
发明人： Chang-Woo Oh , Dong-Gun Park , Jeong-Dong Choe , Kyoung-Hwan Yeo
IPC分类号： H01L21/337
CPC分类号： H01L29/66651 , H01L27/10873 , H01L29/0653 , H01L29/66659
摘要： A semiconductor device employs an asymmetrical buried insulating layer, and a method of fabricating the same. The semiconductor device includes a lower semiconductor substrate. An upper silicon pattern is located on the lower semiconductor substrate. The upper silicon pattern includes a channel region, and a source region and a drain region spaced apart from each other by the channel region. A gate electrode is electrically insulated from the upper silicon pattern and intersects over the channel region. A bit line and a cell capacitor are electrically connected to the source region and the drain region, respectively. A buried insulating layer is interposed between the drain region and the lower semiconductor substrate. The buried insulating layer has an extension portion partially interposed between the channel region and the lower semiconductor substrate.
摘要翻译：半导体器件采用非对称埋层绝缘层及其制造方法。半导体器件包括下半导体衬底。上硅图案位于下半导体衬底上。上部硅图案包括通道区域以及由沟道区域彼此间隔开的源极区域和漏极区域。栅电极与上硅图案电绝缘，并且在沟道区域上相交。位线和单元电容器分别电连接到源极区域和漏极区域。掩埋绝缘层插入在漏区和下半导体衬底之间。掩埋绝缘层具有部分插入在沟道区域和下半导体衬底之间的延伸部分。

5. 发明申请

US20100109087A1 Multichannel Metal Oxide Semiconductor (MOS) Transistors 审中-公开
标题翻译：多通道金属氧化物半导体（MOS）晶体管
公开(公告)号：US20100109087A1
公开(公告)日：2010-05-06
申请号：US12687613
申请日：2010-01-14
申请人： Kyoung-Hwan Yeo , Dong-Gun Park , Jeong-Dong Choe
发明人： Kyoung-Hwan Yeo , Dong-Gun Park , Jeong-Dong Choe
IPC分类号： H01L29/78
CPC分类号： H01L29/66484 , H01L21/8221 , H01L21/823412 , H01L27/0688 , H01L29/7831
摘要： Unit cells of metal oxide semiconductor (MOS) transistors are provided including an integrated circuit substrate an a MOS transistor on the integrated circuit substrate. The MOS transistor includes a source region, a drain region and a gate. The gate is positioned between the source region and the drain region. A horizontal channel is provided between the source and drain regions. The horizontal channel includes at least two spaced apart horizontal channel regions. Related methods of fabricating MOS transistors are also provided.
摘要翻译：提供金属氧化物半导体（MOS）晶体管的单元电池，其包括集成电路基板和集成电路基板上的MOS晶体管。 MOS晶体管包括源极区，漏极区和栅极。栅极位于源极区域和漏极区域之间。在源区和漏区之间提供水平通道。水平通道包括至少两个间隔开的水平通道区域。还提供了制造MOS晶体管的相关方法。

6. 发明申请

US20100237401A1 GATE STRUCTURES OF SEMICONDUCTOR DEVICES 审中-公开
标题翻译：半导体器件的门结构
公开(公告)号：US20100237401A1
公开(公告)日：2010-09-23
申请号：US12726836
申请日：2010-03-18
申请人： JEONG-DONG CHOE , Kyoung-Sub Shin , Kyoung-Hwan Yeo
发明人： JEONG-DONG CHOE , Kyoung-Sub Shin , Kyoung-Hwan Yeo
IPC分类号： H01L29/792
CPC分类号： H01L29/792 , H01L27/11568 , H01L29/40117 , H01L29/513
摘要： Gate structures of semiconductor devices and methods of forming gate structures of semiconductor devices are provided. A first insulating pattern may be disposed on an active region of a semiconductor substrate. A data storage pattern may be disposed on the first insulating pattern. A second insulating pattern may be disposed on the data storage pattern and may contact the data storage pattern. A first conductive pattern may conform to the second insulating pattern and to sidewalls of a mold comprising the second insulating pattern. A second conductive pattern may be disposed within a cavity defined by the first conductive pattern. Spacers may be formed on sidewalls of at least one of the first insulating pattern, the data storage pattern, the second insulating pattern, and the conductive pattern.
摘要翻译：提供了半导体器件的栅极结构和形成半导体器件的栅极结构的方法。第一绝缘图案可以设置在半导体衬底的有源区上。数据存储图案可以设置在第一绝缘图案上。第二绝缘图案可以设置在数据存储图案上并且可以接触数据存储图案。第一导电图案可以符合第二绝缘图案以及包括第二绝缘图案的模具的侧壁。第二导电图案可以设置在由第一导电图案限定的空腔内。间隔件可以形成在第一绝缘图案，数据存储图案，第二绝缘图案和导电图案中的至少一个的侧壁上。

7. 发明申请

US20080194065A1 INTEGRATED CIRCUIT DEVICES HAVING AN EPITAXIAL PATTERN WITH A VOID REGION FORMED THEREIN AND METHODS OF FORMING THE SAME 审中-公开
标题翻译：具有形成有空位区域的外延图案的集成电路装置及其形成方法
公开(公告)号：US20080194065A1
公开(公告)日：2008-08-14
申请号：US12107468
申请日：2008-04-22
申请人： Sung-Young Lee , Sung-Min Kim , Dong-Gun Park , Kyoung-Hwan Yeo
发明人： Sung-Young Lee , Sung-Min Kim , Dong-Gun Park , Kyoung-Hwan Yeo
IPC分类号： H01L21/02
CPC分类号： H01L29/66651 , H01L21/76224 , H01L21/76289 , H01L21/764 , H01L29/0649 , H01L29/66795 , H01L29/785 , H01L29/78603 , H01L29/802
摘要： An integrated circuit device includes a substrate. An epitaxial pattern is on the substrate and has a pair of impurity diffusion regions formed therein and a pair of void regions formed therein that are disposed between the pair of impurity diffusion regions and the substrate. Respective ones of the pair of impurity diffusion regions at least partially overlap respective ones of the pair of void regions. A gate electrode is on the epitaxial pattern between respective ones of the pair of impurity diffusion regions.
摘要翻译：集成电路器件包括衬底。外延图案位于基板上，并且在其间形成有一对杂质扩散区域和形成在其中的一对空隙区域，其设置在该对杂质扩散区域和基板之间。该对杂质扩散区域中的各一个至少部分地重叠该对空隙区域中的相应的一个。栅极电极位于一对杂质扩散区域中的各自之间的外延图案上。

8. 发明授权

US08101475B2 Field effect transistor and method for manufacturing the same 有权
标题翻译：场效应晶体管及其制造方法
公开(公告)号：US08101475B2
公开(公告)日：2012-01-24
申请号：US12588193
申请日：2009-10-07
申请人： Chang-Woo Oh , Dong-Gun Park , Dong-Won Kim , Dong-Uk Choi , Kyoung-Hwan Yeo
发明人： Chang-Woo Oh , Dong-Gun Park , Dong-Won Kim , Dong-Uk Choi , Kyoung-Hwan Yeo
IPC分类号： H01L21/00
CPC分类号： H01L29/0847 , H01L29/1054 , H01L29/665 , H01L29/66621 , H01L29/66636 , H01L29/66651 , H01L29/66795 , H01L29/7851 , H01L29/78687 , H01L29/7881
摘要： A field effect transistor (FET) and a method for manufacturing the same, in which the FET may include an isolation film formed on a semiconductor substrate to define an active region, and a gate electrode formed on a given portion of the semiconductor substrate. A channel layer may be formed on a portion of the gate electrode, with source and drain regions formed on either side of the channel layer so that boundaries between the channel layer and the source and drain regions of the FET may be perpendicular to a surface of the semiconductor substrate.
摘要翻译：场效应晶体管（FET）及其制造方法，其中FET可以包括形成在半导体衬底上以形成有源区的隔离膜，以及形成在半导体衬底的给定部分上的栅电极。沟道层可以形成在栅电极的一部分上，源极和漏极区形成在沟道层的任一侧上，使得沟道层与FET的源极和漏极区之间的边界可以垂直于半导体衬底。

9. 发明申请

US20120058613A1 FIELD EFFECT TRANSISTOR AND METHOD FOR MANUFACTURING THE SAME 有权
标题翻译：场效应晶体管及其制造方法
公开(公告)号：US20120058613A1
公开(公告)日：2012-03-08
申请号：US13284889
申请日：2011-10-29
申请人： Chang-Woo Oh , Dong-Gun Park , Dong-Won Kim , Dong-Uk Choi , Kyoung-Hwan Yeo
发明人： Chang-Woo Oh , Dong-Gun Park , Dong-Won Kim , Dong-Uk Choi , Kyoung-Hwan Yeo
IPC分类号： H01L21/336
CPC分类号： H01L29/0847 , H01L29/1054 , H01L29/665 , H01L29/66621 , H01L29/66636 , H01L29/66651 , H01L29/66795 , H01L29/7851 , H01L29/78687 , H01L29/7881
摘要： A field effect transistor (FET) and a method for manufacturing the same, in which the FET may include an isolation film formed on a semiconductor substrate to define an active region, and a gate electrode formed on a given portion of the semiconductor substrate. A channel layer may be formed on a portion of the gate electrode, with source and drain regions formed on either side of the channel layer so that boundaries between the channel layer and the source and drain regions of the FET may be perpendicular to a surface of the semiconductor substrate.
摘要翻译：场效应晶体管（FET）及其制造方法，其中FET可以包括形成在半导体衬底上以形成有源区的隔离膜，以及形成在半导体衬底的给定部分上的栅电极。沟道层可以形成在栅电极的一部分上，源极和漏极区形成在沟道层的任一侧上，使得沟道层与FET的源极和漏极区之间的边界可以垂直于半导体衬底。

10. 发明申请

US20100035398A1 Field effect transistor and method for manufacturing the same 有权
标题翻译：场效应晶体管及其制造方法
公开(公告)号：US20100035398A1
公开(公告)日：2010-02-11
申请号：US12588193
申请日：2009-10-07
申请人： Chang-Woo Oh , Dong-Gun Park , Dong-Won Kim , Dong-Uk Choi , Kyoung-Hwan Yeo
发明人： Chang-Woo Oh , Dong-Gun Park , Dong-Won Kim , Dong-Uk Choi , Kyoung-Hwan Yeo
IPC分类号： H01L21/336
CPC分类号： H01L29/0847 , H01L29/1054 , H01L29/665 , H01L29/66621 , H01L29/66636 , H01L29/66651 , H01L29/66795 , H01L29/7851 , H01L29/78687 , H01L29/7881
摘要： A field effect transistor (FET) and a method for manufacturing the same, in which the FET may include an isolation film formed on a semiconductor substrate to define an active region, and a gate electrode formed on a given portion of the semiconductor substrate. A channel layer may be formed on a portion of the gate electrode, with source and drain regions formed on either side of the channel layer so that boundaries between the channel layer and the source and drain regions of the FET may be perpendicular to a surface of the semiconductor substrate.
摘要翻译：场效应晶体管（FET）及其制造方法，其中FET可以包括形成在半导体衬底上以形成有源区的隔离膜，以及形成在半导体衬底的给定部分上的栅电极。沟道层可以形成在栅电极的一部分上，源极和漏极区形成在沟道层的任一侧上，使得沟道层与FET的源极和漏极区之间的边界可以垂直于半导体衬底。

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