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1. 发明申请

US20060141716A1 Method for manufacturing a cell transistor of a semiconductor memory device 失效
标题翻译：半导体存储器件的单元晶体管的制造方法
公开(公告)号：US20060141716A1
公开(公告)日：2006-06-29
申请号：US11150026
申请日：2005-06-10
申请人： Kyoung-Bong Rouh , Seung Jin , Min Lee
发明人： Kyoung-Bong Rouh , Seung Jin , Min Lee
IPC分类号： H01L21/336
CPC分类号： H01L29/66575 , H01L27/10873 , H01L29/66492
摘要： Disclosed is a method for manufacturing a cell transistor of a semiconductor memory device. The method comprises the steps of: forming device isolation films and a well on a semiconductor substrate; forming a threshold voltage adjust region by ion-implanting a first conductive impurity dopant into the well of the semiconductor substrate; performing a first thermal annealing on the semiconductor substrate where the threshold voltage adjust region is formed; forming a gate insulating film and gate electrodes on top of the semiconductor substrate between the device isolation films; forming a halo ion implantation region by ion-implanting a first conductive impurity dopant into the semiconductor substrate corresponding to a drain region exposed by the gate electrodes; performing a second thermal annealing on the semiconductor substrate where the halo ion implantation region is formed; and forming source/drain regions by ion-implanting a second conductive impurity dopant into the semiconductor substrate exposed by the gate electrodes. This method can reduce the turn-off leakage current of the cell transistor since the dopant dose of the threshold voltage adjust region can be reduced while maintaining the threshold voltage by increasing the dopant diffusion of the threshold voltage adjust region.
摘要翻译：公开了半导体存储器件的单元晶体管的制造方法。该方法包括以下步骤：在半导体衬底上形成器件隔离膜和阱; 通过将第一导电杂质掺杂剂离子注入到所述半导体衬底的阱中来形成阈值电压调整区域; 在形成有阈值电压调整区域的半导体衬底上进行第一热退火; 在半导体衬底的顶部在器件隔离膜之间形成栅极绝缘膜和栅电极; 通过将第一导电杂质掺杂剂离子注入对应于由栅电极暴露的漏区的半导体衬底中形成晕圈离子注入区; 在形成有所述卤素离子注入区域的所述半导体衬底上进行第二热退火; 以及通过将第二导电杂质掺杂剂离子注入到由所述栅电极暴露的所述半导体衬底中来形成源/漏区。该方法可以减小单元晶体管的截止漏电流，因为阈值电压调整区域的掺杂剂剂量可以通过增加阈值电压调整区域的掺杂剂扩散来维持阈值电压而降低。

2. 发明申请

US20080096353A1 SEMICONDUCTOR DEVICE HAVING A RECESSED GATE AND ASYMMETRIC DOPANT REGIONS AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译：具有阻挡门和不对称区域的半导体器件及其制造方法
公开(公告)号：US20080096353A1
公开(公告)日：2008-04-24
申请号：US11962099
申请日：2007-12-21
申请人： Kyoung Bong Rouh , Seung Jin , Min Lee
发明人： Kyoung Bong Rouh , Seung Jin , Min Lee
IPC分类号： H01L21/336
CPC分类号： H01L29/7834 , H01L29/66621 , H01L29/66636
摘要： A semiconductor device, having a recessed gate and asymmetric dopant regions, comprises a semiconductor substrate having a trench with a first sidewall and a second sidewall, the heights of which are different from each other, a gate insulating layer pattern disposed on the semiconductor substrate, a gate stack disposed on the semiconductor such that the gate stack protrudes from the surface of the semiconductor substrate while the gate stack fills the trench, and first and second dopant regions disposed at the upper part of the semiconductor substrate adjacent to the first and second sidewalls of the trench, respectively, such that the first and second dopant regions have different steps.
摘要翻译：具有凹入栅极和不对称掺杂区域的半导体器件包括具有第一侧壁和第二侧壁的沟槽的半导体衬底，其高度彼此不同，设置在半导体衬底上的栅极绝缘层图案，设置在所述半导体上的栅极堆叠，使得所述栅极堆叠在所述栅极堆叠填充所述沟槽的同时从所述半导体衬底的表面突出;以及设置在所述半导体衬底的与所述第一和第二侧壁相邻的所述上部的第一和第二掺杂剂区域分别使得第一和第二掺杂剂区域具有不同的步骤。

3. 发明申请

US20070120182A1 Transistor having recess gate structure and method for fabricating the same 审中-公开
标题翻译：具有凹槽栅结构的晶体管及其制造方法
公开(公告)号：US20070120182A1
公开(公告)日：2007-05-31
申请号：US11450118
申请日：2006-06-09
申请人： Kyoung Rouh , Seung Jin , Min Lee , Yong Jung
发明人： Kyoung Rouh , Seung Jin , Min Lee , Yong Jung
IPC分类号： H01L29/94
CPC分类号： H01L29/4236 , H01L21/26586 , H01L21/28061 , H01L29/1041 , H01L29/516 , H01L29/66621
摘要： A transistor having a recess gate structure and a method for fabricating the same. The transistor includes a gate insulating layer formed on the inner walls of first trenches formed in a semiconductor substrate; a gate conductive layer formed on the gate insulating layer for partially filling the first trenches; gate electrodes formed on the gate conductive layer for completely filling the first trenches, and surrounded by the gate conductive layer; channel regions formed in the semiconductor substrate along the first trenches; and source/drain regions formed in a shallow portion of the semiconductor substrate.
摘要翻译：具有凹陷栅极结构的晶体管及其制造方法。晶体管包括形成在形成在半导体衬底中的第一沟槽的内壁上的栅极绝缘层; 形成在所述栅极绝缘层上以部分地填充所述第一沟槽的栅极导电层; 栅极电极，形成在栅极导电层上，用于完全填充第一沟槽，并被栅极导电层包围; 形成在半导体衬底中的第一沟槽区; 以及形成在半导体衬底的浅部中的源极/漏极区域。

4. 发明申请

US20070004151A1 Semiconductor device having a recessed gate and asymmetric dopant regions and method of manufacturing the same 有权
标题翻译：具有凹陷栅极和非对称掺杂剂区域的半导体器件及其制造方法
公开(公告)号：US20070004151A1
公开(公告)日：2007-01-04
申请号：US11292381
申请日：2005-11-29
申请人： Kyoung Rouh , Seung Jin , Min Lee
发明人： Kyoung Rouh , Seung Jin , Min Lee
IPC分类号： H01L21/336 , H01L29/788
CPC分类号： H01L29/7834 , H01L29/66621 , H01L29/66636
摘要： A semiconductor device, having a recessed gate and asymmetric dopant regions, comprises a semiconductor substrate having a trench with a first sidewall and a second sidewall, the heights of which are different from each other, a gate insulating layer pattern disposed on the semiconductor substrate, a gate stack disposed on the semiconductor such that the gate stack protrudes from the surface of the semiconductor substrate while the gate stack fills the trench, and first and second dopant regions disposed at the upper part of the semiconductor substrate adjacent to the first and second sidewalls of the trench, respectively, such that the first and second dopant regions have different steps.
摘要翻译：具有凹入栅极和不对称掺杂区域的半导体器件包括具有第一侧壁和第二侧壁的沟槽的半导体衬底，其高度彼此不同，设置在半导体衬底上的栅极绝缘层图案，设置在所述半导体上的栅极堆叠，使得所述栅极堆叠在所述栅极堆叠填充所述沟槽的同时从所述半导体衬底的表面突出;以及设置在所述半导体衬底的与所述第一和第二侧壁相邻的所述上部的第一和第二掺杂剂区域分别使得第一和第二掺杂剂区域具有不同的步骤。

5. 发明申请

US20060252217A1 Non-uniform ion implantation apparatus and method thereof 失效
公开(公告)号：US20060252217A1
公开(公告)日：2006-11-09
申请号：US11305790
申请日：2005-12-16
申请人： Kyoung Rouh , Seung Jin , Min Lee
发明人： Kyoung Rouh , Seung Jin , Min Lee
IPC分类号： H01L21/331
CPC分类号： H01J37/3171 , H01L21/265
摘要： A non-uniform ion implantation apparatus comprises a wide ion beam generator configured to generate a plurality of wide ion beams to irradiate at least two regions on the entire area of a wafer, and a wafer rotating device configured to rotate the wafer in a predetermined direction while the wide ion beams generated by the wide ion beam generator are irradiated to the wafer. Among the wide ion beams, at least one wide ion beam has a different dose from that of at least one different wide ion beam. Since the wide ion beams are irradiated at different doses to the wafer, a smooth circular border is formed between the regions to which the impurity ions are implanted to different concentrations. Since the position of the wafer is suitably changed for the wide ion beams, it is possible to control disposition of the regions implanted with the impurity ions of different concentrations.

6. 发明申请

US20060141690A1 Method for manufacturing a semiconductor device 有权
标题翻译：半导体器件的制造方法
公开(公告)号：US20060141690A1
公开(公告)日：2006-06-29
申请号：US11201843
申请日：2005-08-11
申请人： Seung Jin , Min Lee , Kyoung Rouh
发明人： Seung Jin , Min Lee , Kyoung Rouh
IPC分类号： H01L21/8238 , H01L21/425
CPC分类号： H01L21/28035 , H01L21/26513 , H01L21/823842 , Y10S438/918
摘要： Provided is a method for manufacturing a semiconductor device comprising forming a device isolation layer on a semiconductor substrate; forming gate insulating layers on the upper part of the semiconductor substrate having the device isolation layers formed thereon; forming an undoped layer for a gate electrode; implanting mixed dopant ions consisting of at least two dopant ions containing 11B ions into the undoped layer, utilizing an ion-implantation mask; and heat-treating the mixed dopant ion-implanted layer.
摘要翻译：提供一种半导体器件的制造方法，包括在半导体衬底上形成器件隔离层; 在其上形成有器件隔离层的半导体衬底的上部形成栅极绝缘层; 形成用于栅电极的未掺杂层; 使用离子注入掩模将包含至少两种含有11+ B离子的掺杂剂离子组成的混合掺杂剂离子注入到未掺杂的层中; 并对混合掺杂剂离子注入层进行热处理。

7. 发明申请

US20070065999A1 Method for manufacturing semiconductor memory device using asymmetric junction ion implantation 失效
标题翻译：使用不对称结离子注入制造半导体存储器件的方法
公开(公告)号：US20070065999A1
公开(公告)日：2007-03-22
申请号：US11450816
申请日：2006-06-09
申请人： Min Lee , Kyoung Rouh , Seung Jin
发明人： Min Lee , Kyoung Rouh , Seung Jin
IPC分类号： H01L21/338 , H01L21/8234 , H01L21/336
CPC分类号： H01L27/10855 , H01L27/10876 , H01L27/10888 , H01L29/1037 , H01L29/66621 , H01L29/66659
摘要： A method for manufacturing a semiconductor memory device using asymmetric junction ion implantation, including performing ion implantation for adjusting a threshold voltage to a semiconductor substrate, forming a gate stack on the semiconductor substrate to define a storage node junction region and a bit line junction region, implanting a first conductive impurity ion and a second conductive impurity ion using a mask layer pattern covering the storage node junction region while exposing the bit line junction region, forming a gate spacer layer at both sides of the gate stack, and implanting the first conductive impurity ion using the gate stack and the gate spacer layer as an ion implantation mask layer to form a storage node junction region and a bit line junction region having different impurity concentrations, and different junction depths from each other.
摘要翻译：一种制造使用非对称结离子注入的半导体存储器件的方法，包括执行用于调整对半导体衬底的阈值电压的离子注入，在半导体衬底上形成栅叠层以限定存储节点结区域和位线结区域，使用覆盖存储节点结区域的掩模层图案注入第一导电杂质离子和第二导电杂质离子，同时暴露位线结区域，在栅极堆叠的两侧形成栅极间隔层，以及注入第一导电杂质使用栅极堆叠和栅极间隔层作为离子注入掩模层，以形成具有不同杂质浓度和不同结深度的存储节点结区域和位线结区域。

8. 发明申请

US20070004159A1 Method of manufacturing semiconductor device using gate-through ion implantation 有权
标题翻译：使用栅极通过离子注入制造半导体器件的方法
公开(公告)号：US20070004159A1
公开(公告)日：2007-01-04
申请号：US11272542
申请日：2005-11-10
申请人： Seung Jin , Min Lee , Kyoung Rouh
发明人： Seung Jin , Min Lee , Kyoung Rouh
IPC分类号： H01L21/336
CPC分类号： H01L21/2652 , H01L21/823807 , H01L21/823814 , H01L21/823892 , H01L29/105 , H01L29/6659
摘要： Disclosed herein is a method of manufacturing a semiconductor device via gate-through ion implantation, comprising forming a gate stack on a semiconductor substrate and performing ion implantation for control of the threshold voltage and junction ion implantation for formation of source/drain regions, on the entire surface of the semiconductor substrate having the gate stack formed thereon. In accordance with the present invention, since ion implantation is carried out after formation of the gate stack involving a thermal process, there are no changes in concentrations of implanted dopants due to heat treatment upon formation of the gate stack.
摘要翻译：本文公开了一种通过栅极通过离子注入制造半导体器件的方法，包括在半导体衬底上形成栅极堆叠并执行离子注入以控制用于形成源极/漏极区域的阈值电压和结离子注入半导体衬底的整个表面上形成有栅极叠层。根据本发明，由于在形成包括热处理的栅叠层之后进行离子注入，所以在形成栅叠层时，由于热处理，注入的掺杂剂的浓度没有变化。

9. 发明申请

US20080016834A1 Detachable dustproof filtering device 审中-公开
标题翻译：可拆卸防尘过滤装置
公开(公告)号：US20080016834A1
公开(公告)日：2008-01-24
申请号：US11488658
申请日：2006-07-19
申请人： Min Lee
发明人： Min Lee
IPC分类号： B01D50/00
CPC分类号： B01D46/10 , B01D2279/45
摘要： A detachable dustproof filtering device for network chassis is disclosed. The detachable dustproof filtering device includes a detachable filter cover and a filter. The filter cover is a sheet that breaths and its shape is designed according to the shape of the air inlet of the network chassis. By a connecting member, the filter cover is covered on outside of the air inlet while the filter is disposed on inner surface of the detachable filter cover, covering the air inlet completely. Air drawn by a fan passes through the filter first and then enters inner space of the chassis so that space inside the chassis keeps clean even being used for quite a long time.
摘要翻译：公开了一种用于网络机箱的可拆卸防尘过滤装置。可拆卸的防尘过滤装置包括可拆卸的过滤器盖和过滤器。过滤器盖是呼吸的片材，其形状根据网络底盘的进气口的形状设计。通过连接构件，过滤器盖被覆盖在进气口的外侧，同时过滤器设置在可拆卸过滤器盖的内表面上，完全覆盖进气口。由风扇抽出的空气首先通过过滤器，然后进入机箱的内部空间，使得机箱内的空间即使长时间使用也保持干净。

10. 发明申请

US20070262706A1 New Compound and Organic Light Emitting Device Using the Same 有权
公开(公告)号：US20070262706A1
公开(公告)日：2007-11-15
申请号：US11661391
申请日：2005-09-23
申请人： Seok Yoon , Jae Moon , In Hwang , Min Lee , Wook Cho , Ji Kim , Byung Jeon
发明人： Seok Yoon , Jae Moon , In Hwang , Min Lee , Wook Cho , Ji Kim , Byung Jeon
IPC分类号： H01J1/00
CPC分类号： H01L51/006 , C07D221/20 , C09K11/06 , C09K2211/1022 , C09K2211/1029 , C09K2211/1458 , C09K2211/1466 , H01L51/0058 , H01L51/0061 , H01L51/0072 , H01L51/5012 , H01L51/5048 , H01L51/5088 , H05B33/14 , Y10S428/917
摘要： Disclosed is an organic light emitting device. The organic light emitting device comprises a first electrode, organic material layer(s) comprising a light emitting layer, and a second electrode. The first electrode, the organic material layer(s), and the second electrode form layered structure and at least one layer of the organic material layer(s) include the compound of Formula 1 or the compound of Formula 1 into which a thermosetting or photo-crosslinkable functional group is introduced.

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