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1. 发明授权

US08738838B2 Method, device and system for storing data in storage media using a reference condition 有权
标题翻译：使用参考条件在存储介质中存储数据的方法，设备和系统
公开(公告)号：US08738838B2
公开(公告)日：2014-05-27
申请号：US13082190
申请日：2011-04-07
申请人： Kyoung Lae Cho , Chanho Yoon , JunJin Kong , Hee Chang Cho , Bumseok Yu , Hong Rak Son
发明人： Kyoung Lae Cho , Chanho Yoon , JunJin Kong , Hee Chang Cho , Bumseok Yu , Hong Rak Son
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28
CPC分类号： H03M7/30 , G11C16/349
摘要： A method of storing data in a storage media can include determining whether a size of data to be stored in the storage media satisfies a reference condition and compressing the data to provide compressed data for storage in the storage media upon determining that the size satisfies a reference condition.
摘要翻译：在存储介质中存储数据的方法可以包括确定要存储在存储介质中的数据的大小是否满足参考条件，并且在确定尺寸满足参考值时，压缩数据以提供用于存储在存储介质中的压缩数据条件。

2. 发明授权

US08423878B2 Memory controller and memory system including the same having interface controllers generating parity bits 有权
标题翻译：包括具有产生奇偶校验位的接口控制器的存储器控制器和存储器系统
公开(公告)号：US08423878B2
公开(公告)日：2013-04-16
申请号：US12758103
申请日：2010-04-12
申请人： WooSeong Cheong , Bumseok Yu , Chanho Yoon
发明人： WooSeong Cheong , Bumseok Yu , Chanho Yoon
IPC分类号： G06F11/00
CPC分类号： H03M13/47 , G06F11/10 , H03M13/6306
摘要： A memory controller includes first and second interface controllers configured to exchange data with external devices, and an internal block connected between the first and second interface controllers. The first and second interface controllers exchange data received from the external devices and at least one parity bit corresponding to the received data through the internal block.
摘要翻译：存储器控制器包括被配置为与外部设备交换数据的第一和第二接口控制器以及连接在第一和第二接口控制器之间的内部块。第一和第二接口控制器通过内部块交换从外部设备接收的数据和对应于接收到的数据的至少一个奇偶校验位。

3. 发明申请

US20100306631A1 MEMORY CONTROLLER AND MEMORY SYSTEM INCLUDING THE SAME 有权
标题翻译：内存控制器和存储器系统，包括它们
公开(公告)号：US20100306631A1
公开(公告)日：2010-12-02
申请号：US12758103
申请日：2010-04-12
申请人： WooSeong Cheong , Bumseok Yu , Chanho Yoon
发明人： WooSeong Cheong , Bumseok Yu , Chanho Yoon
IPC分类号： H03M13/09 , G06F12/00 , G06F11/10
CPC分类号： H03M13/47 , G06F11/10 , H03M13/6306
摘要： A memory controller includes first and second interface controllers configured to exchange data with external devices, and an internal block connected between the first and second interface controllers. The first and second interface controllers exchange data received from the external devices and at least one parity bit corresponding to the received data through the internal block.
摘要翻译：存储器控制器包括被配置为与外部设备交换数据的第一和第二接口控制器以及连接在第一和第二接口控制器之间的内部块。第一和第二接口控制器通过内部块交换从外部设备接收的数据和对应于接收到的数据的至少一个奇偶校验位。

4. 发明申请

US20100037119A1 APPARATUS AND METHOD FOR UPDATING CHECK NODE OF LOW-DENSITY PARITY CHECK CODES 审中-公开
标题翻译：检查低密度奇偶校验码代码的装置和方法
公开(公告)号：US20100037119A1
公开(公告)日：2010-02-11
申请号：US12517455
申请日：2007-12-05
申请人： Jong-Ee Oh , Yu-Ro Lee , Chanho Yoon , Minho Cheong , Sok-Kyu Lee , Yoo-Seung Song , Younggyun Kim
发明人： Jong-Ee Oh , Yu-Ro Lee , Chanho Yoon , Minho Cheong , Sok-Kyu Lee , Yoo-Seung Song , Younggyun Kim
IPC分类号： H03M13/05 , G06F11/10
CPC分类号： H03M13/1122 , H03M13/1117 , H03M13/112 , H03M13/6527 , H03M13/6544 , H03M13/6577 , H03M13/658 , H03M13/6583
摘要： An apparatus and method for updating a check node of a low-density parity check (LDPC) code in order to decode the LDPC code are provided. The method includes the operations of: (a) obtaining a first bit of a first minimum value among input values, the number of input values being equal to the number of degrees of the check node, by performing an AND operation on first bits of the input values, the first bits being most significant bits of the input values; (b) obtaining result values by switching and sequentially performing an XOR operation and an OR operation on the first bit of the first minimum value and each of the first bits of the input values; and (c) performing operations (a) and (b) on the result values set as input values and performing operations (a) and (b) a number of times corresponding to the number of bits of each input value, that is, repeating until last bits are set as input values, to thereby obtain the first minimum value, the last bits being least significant bits of the input values. Accordingly, the complexity of hardware is reduced, and super high-speed processing is possible.
摘要翻译：提供了一种用于更新低密度奇偶校验（LDPC）码的校验节点以便解码LDPC码的装置和方法。该方法包括以下操作：（a）通过对所述校验节点的第一比特执行“与”运算，获得输入值中的第一最小值的第一比特，输入值的数目等于校验节点的度数。输入值，第一位是输入值的最高有效位; （b）通过对所述第一最小值的所述第一位和所述输入值的所述第一位中的每一个进行切换和顺序执行异或运算和或运算来获得结果值; 和（c）对设置为输入值的结果值执行操作（a）和（b），并且执行操作（a）和（b）与每个输入值的位数相对应的次数，即重复直到最后的位被设置为输入值为止，从而获得第一最小值，最后的位是输入值的最低有效位。因此，硬件的复杂度降低，超高速处理成为可能。

5. 发明授权

US08295195B2 Apparatus and method for discriminating frame format in wireless communication system 失效
标题翻译：在无线通信系统中识别帧格式的装置和方法
公开(公告)号：US08295195B2
公开(公告)日：2012-10-23
申请号：US12642167
申请日：2009-12-18
申请人： Chanho Yoon , Il-Gu Lee , Jung-Bo Son , Sok-Kyu Lee
发明人： Chanho Yoon , Il-Gu Lee , Jung-Bo Son , Sok-Kyu Lee
IPC分类号： H04L12/26 , H04J3/16
CPC分类号： H04L1/0038 , H04L5/0007 , H04L27/0012 , H04L27/2666
摘要： A frame format discrimination method in a wireless communication system is provided. The frame format discrimination method includes: calculating a power of an in-phase signal and a power of a quadrature signal in a predetermined section of a frame; comparing the power of the in-phase signal with the power of the quadrature signal; and determining the format of the frame in accordance with the comparison result.
摘要翻译：提供了一种无线通信系统中的帧格式辨别方法。帧格式识别方法包括：在帧的预定部分中计算同相信号的功率和正交信号的功率; 将同相信号的功率与正交信号的功率进行比较; 以及根据比较结果确定帧的格式。

6. 发明授权

US07804801B2 QR decomposition apparatus and method for MIMO system 失效
标题翻译：用于MIMO系统的QR分解装置和方法
公开(公告)号：US07804801B2
公开(公告)日：2010-09-28
申请号：US12131617
申请日：2008-06-02
申请人： Yu-Ro Lee , Byung-Chan Kim , Minho Cheong , Chanho Yoon , Je-Hun Lee , Kwhang-Hyun Ryu , Cheol-Jung Kim , Tae-Hyun Jeon , Sok-Kyu Lee
发明人： Yu-Ro Lee , Byung-Chan Kim , Minho Cheong , Chanho Yoon , Je-Hun Lee , Kwhang-Hyun Ryu , Cheol-Jung Kim , Tae-Hyun Jeon , Sok-Kyu Lee
IPC分类号： H04W4/00
CPC分类号： H04L25/0246 , H04L25/03006 , H04L2025/03414 , H04L2025/03426
摘要： Provided are a QR decomposition apparatus and method for a MIMO system. The QR decomposition apparatus includes: a norm calculator for calculating a vector size norm for a channel input; a Q column calculator for calculating a column value of a unitary matrix Q by multiplying a delayed channel input with √{square root over (norm)}; an R row calculator for receiving the delayed channel input, the output of the Q column calculator, and 1/√{square root over (norm)}, and calculating a row value of an upper triangular matrix R; a Q update calculator for receiving the delayed channel input, the output of the R row calculator, and a delayed output of the Q column calculator, and calculating a Q update matrix value; and a norm update calculator for receiving a delayed output of the norm calculator and an output of the R row calculator, and outputting a norm update matrix value.
摘要翻译：提供了一种用于MIMO系统的QR分解装置和方法。 QR分解装置包括：用于计算信道输入的矢量大小范数的范数计算器; Q列计算器，用于通过将延迟的信道输入与{平方根超过（norm）}相乘来计算酉矩阵Q的列值; 用于接收延迟信道输入的R行计算器，Q列计算器的输出和1 /√{平方根超过（norm）}，并计算上三角矩阵R的行值; 用于接收延迟信道输入，R行计算器的输出和Q列计算器的延迟输出的Q更新计算器，并计算Q更新矩阵值; 以及范数更新计算器，用于接收范数计算器的延迟输出和R行计算器的输出，并输出范数更新矩阵值。

7. 发明申请

US20140366153A1 STORAGE DEVICES WITH SECURE DEBUGGING CAPABILITY AND METHODS OF OPERATING THE SAME 有权
标题翻译：具有安全调试能力的存储设备及其操作方法
公开(公告)号：US20140366153A1
公开(公告)日：2014-12-11
申请号：US14465509
申请日：2014-08-21
申请人： Chanho Yoon
发明人： Chanho Yoon
IPC分类号： G06F21/60 , G06F11/273
CPC分类号： G06F21/60 , G06F9/00 , G06F11/00 , G06F11/273 , G06F11/30 , G06F11/3089 , G06F11/362 , G06F11/3648 , G06F13/36 , G06F13/42 , G06F21/00 , G06F21/78 , H04L9/32 , H04L63/00
摘要： A device includes a first bus, a second bus, a processor configured to communicate with a storage circuit through the first bus and to communicate with a debug host through the second bus and a control circuit configured to inhibit transfer of data from the second bus to the debug host while receiving authentication information from the debug host and to enable transfer of data from the second bus to the debug host responsive to authentication of the received authentication information. The control circuit may be configured to inhibit data transfer from the second bus to the debug host by causing dummy data to be transmitted to the debug host over a transmit channel between the device and the debug host.
摘要翻译：一种设备包括第一总线，第二总线，配置成通过第一总线与存储电路通信并通过第二总线与调试主机进行通信的处理器;以及控制电路，其被配置为禁止将数据从第二总线传送到所述调试主机在从所述调试主机接收认证信息的同时，以及响应于所接收的认证信息的认证，使得能够将数据从所述第二总线传送到所述调试主机。控制电路可以被配置为通过使伪数据通过设备和调试主机之间的发送信道发送到调试主机来禁止从第二总线到调试主机的数据传输。

8. 发明授权

US08214717B2 Apparatus and method for decoding LDPC code based on prototype parity check matrixes 失效
标题翻译：基于原型奇偶校验矩阵对LDPC码进行解码的装置和方法
公开(公告)号：US08214717B2
公开(公告)日：2012-07-03
申请号：US12166866
申请日：2008-07-02
申请人： Jong-Ee Oh , Chanho Yoon , Cheol-Hui Ryu , Eun-Young Choi , Sok-Kyu Lee
发明人： Jong-Ee Oh , Chanho Yoon , Cheol-Hui Ryu , Eun-Young Choi , Sok-Kyu Lee
IPC分类号： H03M13/00
CPC分类号： H03M13/116 , H03M13/1137 , H03M13/1185 , H03M13/1188 , H03M13/6516
摘要： Provided is an apparatus and method for decoding a Low Density Parity Check (LDPC) code based on prototype parity check matrixes. The apparatus, includes: a parity check matrix selecting means for determining multiple prototype parity check matrixes according to a sub-matrix size and a parallelization figure for processing the parity check matrix; a bit input means for receiving a log likelihood probability value for input bit according to the sub-matrix size and the parallelization figure; a check matrix process means for sequentially performing a partial parallel process on the parity check matrix based on the received log likelihood probability value and the determined multiple prototype parity check matrixes; and a bit process means for determining a bit level based on the partial-parallel processed parity check matrix value and recovering the input bit according to the sub-matrix size and the parallelization figure.
摘要翻译：提供了一种基于原型奇偶校验矩阵对低密度奇偶校验（LDPC）码进行解码的装置和方法。该装置包括：奇偶校验矩阵选择装置，用于根据子矩阵大小确定多个原型奇偶校验矩阵;以及用于处理奇偶校验矩阵的并行化图; 用于根据子矩阵大小和并行化图形接收输入比特的对数似然概率值的位输入装置; 校验矩阵处理装置，用于基于所接收的对数似然概率值和所确定的多原型奇偶校验矩阵，顺序对奇偶校验矩阵执行部分并行处理; 以及位处理装置，用于基于部分并行处理的奇偶校验矩阵值确定位电平，并根据子矩阵大小和并行化图形恢复输入位。

9. 发明授权

US08107563B2 Receiving apparatus and method for MIMO system 有权
标题翻译： MIMO系统的接收装置和方法
公开(公告)号：US08107563B2
公开(公告)日：2012-01-31
申请号：US12177655
申请日：2008-07-22
申请人： Chanho Yoon , Il-Gu Lee , Jung-Bo Son , Eun-Young Choi , Yu-Ro Lee , Sok-Kyu Lee
发明人： Chanho Yoon , Il-Gu Lee , Jung-Bo Son , Eun-Young Choi , Yu-Ro Lee , Sok-Kyu Lee
IPC分类号： H04L27/14
CPC分类号： H04B7/0851 , H04B7/0669 , H04L1/0048 , H04L1/0631 , H04L25/067 , H04L27/2601
摘要： Provided are a receiving apparatus for a multiple input multiple output (MIMO) system and a method thereof. The receiving apparatus includes a QR decomposing unit for calculating a single (Q) matrix vector and an upper triangle (R) matrix vector for a receiving signal vector; a first symbol estimation unit for estimating predetermined symbols using the calculated Q matrix vector and R matrix vector; a log likelihood ratio (LLR) calculating unit for calculating log likelihood ratios of unit bits for the estimated symbols; an interference removing unit for receiving a decoded signal that is decided using the calculated log likelihood ratios and removing interference from the receiving signal vector; and a second symbol estimation unit for linearly estimating remaining symbols for the interference removed signal.
摘要翻译：提供了一种用于多输入多输出（MIMO）系统的接收装置及其方法。接收装置包括用于计算接收信号矢量的单（Q）矩阵向量和上三角（R）矩阵向量的QR分解单元; 第一符号估计单元，用于使用所计算的Q矩阵向量和R矩阵向量来估计预定符号; 对数似然比（LLR）计算单元，用于计算估计符号的单位比特的对数似然比; 干扰去除单元，用于接收使用所计算的对数似然比决定的解码信号，并从接收信号矢量中去除干扰; 以及用于线性估计用于干扰去除信号的剩余符号的第二符号估计单元。

10. 发明授权

US08832843B2 Storage devices with secure debugging capability and methods of operating the same 有权
标题翻译：具有安全调试功能的存储设备及其操作方法
公开(公告)号：US08832843B2
公开(公告)日：2014-09-09
申请号：US12783953
申请日：2010-05-20
申请人： Chanho Yoon
发明人： Chanho Yoon
IPC分类号： G06F7/04 , G06F17/30 , H04N7/16 , G06F11/30 , G06F11/36 , G06F21/78 , H04L9/32 , G06F11/00 , G06F21/00 , G06F13/36 , G06F9/00 , H04L29/06
CPC分类号： G06F21/60 , G06F9/00 , G06F11/00 , G06F11/273 , G06F11/30 , G06F11/3089 , G06F11/362 , G06F11/3648 , G06F13/36 , G06F13/42 , G06F21/00 , G06F21/78 , H04L9/32 , H04L63/00
摘要： A device includes a first bus, a second bus, a processor configured to communicate with a storage circuit through the first bus and to communicate with a debug host through the second bus and a control circuit configured to inhibit transfer of data from the second bus to the debug host while receiving authentication information from the debug host and to enable transfer of data from the second bus to the debug host responsive to authentication of the received authentication information. The control circuit may be configured to inhibit data transfer from the second bus to the debug host by causing dummy data to be transmitted to the debug host over a transmit channel between the device and the debug host.
摘要翻译：一种设备包括第一总线，第二总线，配置成通过第一总线与存储电路通信并通过第二总线与调试主机进行通信的处理器;以及控制电路，其被配置为禁止将数据从第二总线传送到所述调试主机在从所述调试主机接收认证信息的同时，以及响应于所接收的认证信息的认证，使得能够将数据从所述第二总线传送到所述调试主机。控制电路可以被配置为通过使伪数据通过设备和调试主机之间的发送信道发送到调试主机来禁止从第二总线到调试主机的数据传输。

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