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1. 发明申请

US20110041104A1 Semiconductor circuit pattern design method for manufacturing semiconductor device or liquid crystal display device 审中-公开
标题翻译：用于制造半导体器件或液晶显示器件的半导体电路图案设计方法
公开(公告)号：US20110041104A1
公开(公告)日：2011-02-17
申请号：US12805093
申请日：2010-07-12
申请人： Kyoko Izuha , Fumihiro Minami , Toshiaki Ueda , Ryuji Ogawa , Satoshi Tanaka
发明人： Kyoko Izuha , Fumihiro Minami , Toshiaki Ueda , Ryuji Ogawa , Satoshi Tanaka
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G06F17/5031 , G06F17/5036
摘要： A semiconductor circuit pattern design method includes the following operations. A design pattern is created by placing a plurality of cells in each functional block as a unit of the semiconductor circuit and executing routing among the plurality of placed cells. Mask pattern data based on the design pattern is created. A predictive pattern to be formed on the substrate by the mask pattern data is predicted. A difference amount between the predictive pattern and a target pattern to be formed on the substrate by the mask pattern data is checked. The difference amount is compared with a predetermined allowable variation amount. If the difference amount is larger than the allowable variation amount in the comparison, at least one of placement and routing of the cells in the design pattern corresponding to the mask pattern data used to predict the predictive pattern is corrected.
摘要翻译：半导体电路图案设计方法包括以下操作。通过将每个功能块中的多个单元放置为半导体电路的单元并在多个放置的单元之间执行布线来创建设计图案。创建基于设计模式的掩模图案数据。预测通过掩模图案数据在衬底上形成的预测图案。检查通过掩模图案数据在衬底上形成的预测图案和目标图案之间的差值。将差值与预定的允许变化量进行比较。如果差异量大于比较中允许的变化量，则校正与用于预测预测图案的掩模图案数据相对应的设计图案中的单元的放置和布线中的至少一个。

2. 发明授权

US07784020B2 Semiconductor circuit pattern design method for manufacturing semiconductor device or liquid crystal display device 失效
标题翻译：用于制造半导体器件或液晶显示器件的半导体电路图案设计方法
公开(公告)号：US07784020B2
公开(公告)日：2010-08-24
申请号：US11429077
申请日：2006-05-08
申请人： Kyoko Izuha , Fumihiro Minami , Toshiaki Ueda , Ryuji Ogawa , Satoshi Tanaka
发明人： Kyoko Izuha , Fumihiro Minami , Toshiaki Ueda , Ryuji Ogawa , Satoshi Tanaka
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G06F17/5031 , G06F17/5036
摘要： A semiconductor circuit pattern design method includes the following operations. A design pattern is created by placing a plurality of cells in each functional block as a unit of the semiconductor circuit and executing routing among the plurality of placed cells. Mask pattern data based on the design pattern is created. A predictive pattern to be formed on the substrate by the mask pattern data is predicted. A difference amount between the predictive pattern and a target pattern to be formed on the substrate by the mask pattern data is checked. The difference amount is compared with a predetermined allowable variation amount. If the difference amount is larger than the allowable variation amount in the comparison, at least one of placement and routing of the cells in the design pattern corresponding to the mask pattern data used to predict the predictive pattern is corrected.
摘要翻译：半导体电路图案设计方法包括以下操作。通过将每个功能块中的多个单元放置为半导体电路的单元并在多个放置的单元之间执行布线来创建设计图案。创建基于设计模式的掩模图案数据。预测通过掩模图案数据在衬底上形成的预测图案。检查通过掩模图案数据在衬底上形成的预测图案和目标图案之间的差值。将差值与预定的允许变化量进行比较。如果差异量大于比较中允许的变化量，则校正与用于预测预测图案的掩模图案数据相对应的设计图案中的单元的放置和布线中的至少一个。

3. 发明申请

US20060271907A1 Semiconductor circuit pattern design method for manufacturing semiconductor device or liquid crystal display device 失效
标题翻译：用于制造半导体器件或液晶显示器件的半导体电路图案设计方法
公开(公告)号：US20060271907A1
公开(公告)日：2006-11-30
申请号：US11429077
申请日：2006-05-08
申请人： Kyoko Izuha , Fumihiro Minami , Toshiaki Ueda , Ryuji Ogawa , Satoshi Tanaka
发明人： Kyoko Izuha , Fumihiro Minami , Toshiaki Ueda , Ryuji Ogawa , Satoshi Tanaka
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G06F17/5031 , G06F17/5036
摘要： A semiconductor circuit pattern design method includes the following operations. A design pattern is created by placing a plurality of cells in each functional block as a unit of the semiconductor circuit and executing routing among the plurality of placed cells. Mask pattern data based on the design pattern is created. A predictive pattern to be formed on the substrate by the mask pattern data is predicted. A difference amount between the predictive pattern and a target pattern to be formed on the substrate by the mask pattern data is checked. The difference amount is compared with a predetermined allowable variation amount. If the difference amount is larger than the allowable variation amount in the comparison, at least one of placement and routing of the cells in the design pattern corresponding to the mask pattern data used to predict the predictive pattern is corrected.
摘要翻译：半导体电路图案设计方法包括以下操作。通过将每个功能块中的多个单元放置为半导体电路的单元并在多个放置的单元之间执行布线来创建设计图案。创建基于设计模式的掩模图案数据。预测通过掩模图案数据在衬底上形成的预测图案。检查通过掩模图案数据在衬底上形成的预测图案和目标图案之间的差值。将差值与预定的允许变化量进行比较。如果差异量大于比较中允许的变化量，则校正与用于预测预测图案的掩模图案数据相对应的设计图案中的单元的放置和布线中的至少一个。

4. 发明授权

US07194704B2 Design layout preparing method 有权
标题翻译：设计布局准备方法
公开(公告)号：US07194704B2
公开(公告)日：2007-03-20
申请号：US11012491
申请日：2004-12-16
申请人： Toshiya Kotani , Shigeki Nojima , Suigen Kyoh , Kyoko Izuha , Ryuji Ogawa , Satoshi Tanaka , Soichi Inoue , Hirotaka Ichikawa
发明人： Toshiya Kotani , Shigeki Nojima , Suigen Kyoh , Kyoko Izuha , Ryuji Ogawa , Satoshi Tanaka , Soichi Inoue , Hirotaka Ichikawa
IPC分类号： G06F17/50 , G06F9/45 , G06F9/455
CPC分类号： G06F17/5081 , H01L21/0271
摘要： There is disclosed a method of producing a design layout by optimizing at least one of design rule, process proximity correction parameter and process parameter, including calculating a processed pattern shape based on a design layout and a process parameter, extracting a dangerous spot having an evaluation value with respect to the processed pattern shape, which does not satisfy a predetermined tolerance, generating a repair guideline of the design layout based on a pattern included in the dangerous spot, and repairing that portion of the design layout which corresponds to the dangerous spot based on the repair guideline.
摘要翻译：公开了一种通过优化设计规则，过程接近校正参数和过程参数中的至少一个来生成设计布局的方法，包括基于设计布局和过程参数来计算处理的图案形状，提取具有评估的危险点相对于不满足预定公差的加工图案形状的值，基于包含在危险点中的图案生成设计布局的修理指南，并且修复与危险点对应的设计布局的那部分在维修准则上。

5. 发明申请

US20050204322A1 Design layout preparing method 有权
标题翻译：设计布局准备方法
公开(公告)号：US20050204322A1
公开(公告)日：2005-09-15
申请号：US11012491
申请日：2004-12-16
申请人： Toshiya Kotani , Shigeki Nojima , Suigen Kyoh , Kyoko Izuha , Ryuji Ogawa , Satoshi Tanaka , Soichi Inoue , Hirotaka Ichikawa
发明人： Toshiya Kotani , Shigeki Nojima , Suigen Kyoh , Kyoko Izuha , Ryuji Ogawa , Satoshi Tanaka , Soichi Inoue , Hirotaka Ichikawa
IPC分类号： G03F1/36 , G03F1/68 , G03F1/70 , G06F17/50 , H01L21/027 , H01L21/82
CPC分类号： G06F17/5081 , H01L21/0271
摘要： There is disclosed a method of producing a design layout by optimizing at least one of design rule, process proximity correction parameter and process parameter, including calculating a processed pattern shape based on a design layout and a process parameter, extracting a dangerous spot having an evaluation value with respect to the processed pattern shape, which does not satisfy a predetermined tolerance, generating a repair guideline of the design layout based on a pattern included in the dangerous spot, and repairing that portion of the design layout which corresponds to the dangerous spot based on the repair guideline.
摘要翻译：公开了一种通过优化设计规则，过程接近校正参数和过程参数中的至少一个来生成设计布局的方法，包括基于设计布局和过程参数来计算处理的图案形状，提取具有评估的危险点相对于不满足预定公差的加工图案形状的值，基于包含在危险点中的图案生成设计布局的修理指南，并且修复与危险点对应的设计布局的那部分在维修准则上。

6. 发明授权

US07788626B2 Pattern data correction method, pattern checking method, pattern check program, photo mask producing method, and semiconductor device manufacturing method 有权
标题翻译：图案数据校正方法，图案检查方法，图案检查程序，光掩模制造方法和半导体器件制造方法
公开(公告)号：US07788626B2
公开(公告)日：2010-08-31
申请号：US11138407
申请日：2005-05-27
申请人： Shigeki Nojima , Satoshi Tanaka , Toshiya Kotani , Kyoko Izuha , Soichi Inoue
发明人： Shigeki Nojima , Satoshi Tanaka , Toshiya Kotani , Kyoko Izuha , Soichi Inoue
IPC分类号： G06F17/50
CPC分类号： G03F1/36
摘要： A pattern data correction method is disclosed, which comprises preparing an integrated circuit pattern, setting a tolerance to the pattern that is allowable error range when the pattern is transferred on a substrate, creating a target pattern within the tolerance, and making correction for the target pattern to make a first correction pattern under a predetermined condition.
摘要翻译：公开了一种图案数据校正方法，其包括：准备集成电路图案，在图案在衬底上传送时设定容许误差范围的容许度，在公差内产生目标图案，并对目标进行校正模式以在预定条件下进行第一校正模式。

7. 发明授权

US07200833B2 Calculating method, verification method, verification program and verification system for edge deviation quantity, and semiconductor device manufacturing method 失效
标题翻译：边缘偏移量的计算方法，验证方法，验证程序和验证系统以及半导体器件制造方法
公开(公告)号：US07200833B2
公开(公告)日：2007-04-03
申请号：US10801798
申请日：2004-03-17
申请人： Kyoko Izuha , Toshiya Kotani , Satoshi Tanaka
发明人： Kyoko Izuha , Toshiya Kotani , Satoshi Tanaka
IPC分类号： G06F17/50 , G06K9/00
CPC分类号： G03F7/705
摘要： A method in which a desired pattern is compared with a finish pattern to be formed on a wafer, which is predicted from a design pattern, based on a calculation of a light beam intensity, and a deviation quantity of the finish pattern from the desired pattern at each edge of the finish pattern and the desired pattern is calculated, comprising setting a reference light beam intensity for setting the desired pattern on a wafer, setting an evaluation point for comparison of the finish pattern with the desired pattern, calculating a light beam intensity at the evaluation point, calculating a differentiation value of the light beam intensity at the evaluation point, calculating an intersection of the differentiation value with the reference light beam intensity, and calculating a difference between the intersection and the evaluation point, the difference defining an edge deviation quantity of the finish pattern from the desired pattern.
摘要翻译：将期望图案与根据设计图案预测的要在晶片上形成的光洁度图案进行比较的方法，基于光束强度的计算和完成图案与期望图案的偏差量在完成图案的每个边缘处并计算所需图案，包括设置用于在晶片上设置期望图案的参考光束强度，设置用于将完成图案与期望图案进行比较的评估点，计算光束强度在评价点，计算评价点的光束强度的微分值，计算微分值与参考光束强度的交点，计算交点与评价点之间的差，限定边缘的差完成图案与期望图案的偏差量。

8. 发明申请

US20050153217A1 Pattern verification method, pattern verification system, mask manufacturing method and semiconductor device manufacturing method 失效
标题翻译：模式验证方法，模式验证系统，掩模制造方法和半导体器件制造方法
公开(公告)号：US20050153217A1
公开(公告)日：2005-07-14
申请号：US11012494
申请日：2004-12-16
申请人： Kyoko Izuha , Shigeki Nojima , Toshiya Kotani , Satoshi Tanaka
发明人： Kyoko Izuha , Shigeki Nojima , Toshiya Kotani , Satoshi Tanaka
IPC分类号： G03F1/36 , G03F1/68 , G03F1/70 , G03F7/20 , G03F9/00 , G06F17/50 , H01L21/027
CPC分类号： G03F7/70441 , G03F1/36
摘要： A pattern verification method comprising preparing a desired pattern and a mask pattern forming the desired pattern on a substrate, defining at least one evaluation point on an edge of the desired pattern, defining at least one process parameter to compute the transferred/formed pattern, defining a reference value and a variable range for each of the process parameters, computing a positional displacement for each first points corresponding to the evaluation point, first points computed using correction mask pattern and a plurality of combinations of parameter values obtained by varying the process parameters within the variable range or within the respective variable ranges, the positional displacement being displacement between first point and the evaluation point, computing a statistics of the positional displacements for each of the evaluation points, and outputting information modifying the mask pattern according to the statistics.
摘要翻译：一种图案验证方法，包括在衬底上制备期望图案和形成期望图案的掩模图案，在期望图案的边缘上限定至少一个评估点，限定至少一个工艺参数以计算所转印/形成的图案，定义对于每个过程参数的参考值和可变范围，计算与评估点相对应的每个第一点的位置位移，使用校正掩模图案计算的第一点和通过改变其中的处理参数而获得的参数值的多个组合可变范围或在各个可变范围内，位置偏移是第一点和评估点之间的位移，计算每个评估点的位置偏移的统计，以及根据统计信息输出修改掩模图案的信息。

9. 发明授权

US07631287B2 Calculating method, verification method, verification program and verification system for edge deviation quantity, and semiconductor device manufacturing method 失效
标题翻译：边缘偏移量的计算方法，验证方法，验证程序和验证系统以及半导体器件制造方法
公开(公告)号：US07631287B2
公开(公告)日：2009-12-08
申请号：US11727288
申请日：2007-03-26
申请人： Kyoko Izuha , Toshiya Kotani , Satoshi Tanaka
发明人： Kyoko Izuha , Toshiya Kotani , Satoshi Tanaka
IPC分类号： G06F17/50
CPC分类号： G03F7/705
摘要： A method in which a desired pattern is compared with a finish pattern to be formed on a wafer, which is predicted from a design pattern, based on a calculation of a light beam intensity, and a deviation quantity of the finish pattern from the desired pattern at each edge of the finish pattern and the desired pattern is calculated, comprising setting a reference light beam intensity for setting the desired pattern on a wafer, setting an evaluation point for comparison of the finish pattern with the desired pattern, calculating a light beam intensity at the evaluation point, calculating a differentiation value of the light beam intensity at the evaluation point, calculating an intersection of the differentiation value with the reference light beam intensity, and calculating a difference between the intersection and the evaluation point, the difference defining an edge deviation quantity of the finish pattern from the desired pattern.
摘要翻译：将期望图案与根据设计图案预测的要在晶片上形成的光洁度图案进行比较的方法，基于光束强度的计算和完成图案与期望图案的偏差量在完成图案的每个边缘处并计算所需图案，包括设置用于在晶片上设置期望图案的参考光束强度，设置用于将完成图案与期望图案进行比较的评估点，计算光束强度在评价点，计算评价点的光束强度的微分值，计算微分值与参考光束强度的交点，计算交点与评价点之间的差，限定边缘的差完成图案与期望图案的偏差量。

10. 发明授权

US07571417B2 Method and system for correcting a mask pattern design 失效
标题翻译：用于校正掩模图案设计的方法和系统
公开(公告)号：US07571417B2
公开(公告)日：2009-08-04
申请号：US11012494
申请日：2004-12-16
申请人： Kyoko Izuha , Shigeki Nojima , Toshiya Kotani , Satoshi Tanaka
发明人： Kyoko Izuha , Shigeki Nojima , Toshiya Kotani , Satoshi Tanaka
IPC分类号： G06F17/50
CPC分类号： G03F7/70441 , G03F1/36
摘要： A pattern verification method includes preparing a desired pattern and a mask pattern forming the desired pattern on a substrate, defining at least one evaluation point on an edge of the desired pattern, defining at least one process parameter to compute the transferred/formed pattern, defining a reference value and a variable range for each of the process parameters, and computing a positional displacement for each first points corresponding to the evaluation point, first points computed using correction mask pattern and a plurality of combinations of parameter values obtained by varying the process parameters within the variable range or within the respective variable ranges. The positional displacement is a displacement between first point and the evaluation point. The method further includes computing a statistics of the positional displacements for each of the evaluation points, and outputting information modifying the mask pattern according to the statistics.
摘要翻译：模式验证方法包括在衬底上制备期望图案和形成期望图案的掩模图案，在期望图案的边缘上限定至少一个评估点，限定至少一个过程参数以计算所转移/形成的图案，定义针对每个处理参数的参考值和可变范围，并且计算与评估点相对应的每个第一点的位置偏移，使用校正掩模图案计算的第一点和通过改变处理参数获得的参数值的多个组合在可变范围内或在相应的可变范围内。位置偏移是第一点与评价点之间的位移。该方法还包括计算每个评估点的位置偏移的统计量，并根据统计信息输出修改掩模图案的信息。

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