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1. 发明授权

US06229757B1 Semiconductor memory device capable of securing large latch margin 有权
标题翻译：能够确保大的锁存余量的半导体存储器件
公开(公告)号：US06229757B1
公开(公告)日：2001-05-08
申请号：US09315828
申请日：1999-05-21
申请人： Kyoichi Nagata , Yasuo Kobayashi
发明人： Kyoichi Nagata , Yasuo Kobayashi
IPC分类号： G11C800
CPC分类号： G11C7/1093 , G11C7/1066 , G11C7/1072 , G11C7/1087 , G11C7/22
摘要： In a double data rate type synchronous dynamic random access memory (DDR-SDRAM) device, a large latch margin of input data is secured. The DDR-SDRAM device is arranged by a data strobe signal processing circuit for detecting at least one of a rise edge of a data strobe signal and a fall edge thereof to thereby produce at least a first one-shot pulse signal; a clock signal processing circuit for detecting a rise edge of a clock signal to thereby produce a second one-shot pulse signal; and a data-in processing circuit for latching input data by using the first one-shot pulse signal produced from the data strobe signal, and further for latching the latched input data by using the second one-shot pulse signal produced from the clock signal, and also for simultaneously writing both the latched data into a memory cell in a parallel manner. The data-in processing circuit controls a delay amount of the first one-shot pulse signal and another delay amount of the second one-shot pulse signal so as to secure a latch margin of the input data.
摘要翻译：在双倍数据速率类型的同步动态随机存取存储器（DDR-SDRAM）装置中，确保输入数据的大的锁存边沿。 DDR-SDRAM装置由数据选通信号处理电路配置，用于检测数据选通信号的上升沿及其下降沿中的至少一个，从而产生至少第一单触发脉冲信号; 时钟信号处理电路，用于检测时钟信号的上升沿，从而产生第二单触发脉冲信号; 以及数据输入处理电路，用于通过使用从数据选通信号产生的第一单触发脉冲信号来锁存输入数据，并且还用于通过使用从时钟信号产生的第二单触发脉冲信号来锁存锁存的输入数据，并且还用于以并行方式同时将锁存的数据写入存储器单元。数据输入处理电路控制第一单触发脉冲信号的延迟量和第二单触发脉冲信号的另一延迟量，以确保输入数据的锁存边沿。

2. 发明授权

US09036448B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US09036448B2
公开(公告)日：2015-05-19
申请号：US13415777
申请日：2012-03-08
申请人： Kyoichi Nagata
发明人： Kyoichi Nagata
IPC分类号： G11C8/18 , H03K21/40
CPC分类号： G11C8/18 , H03K21/406
摘要： A device includes a first clock generation circuit that receives an external clock signal supplied to the device, delays the external clock signal to output a first clock signal synchronized with the external clock signal, and a circuit that generates a control signal to control output of data, based on second clock signals obtained by dividing an internal clock signal generated from the external clock signal, and third clock signals obtained by dividing the first clock signal.
摘要翻译：一种设备包括：第一时钟产生电路，其接收提供给该设备的外部时钟信号，延迟外部时钟信号以输出与外部时钟信号同步的第一时钟信号，以及产生控制信号以控制数据输出的电路基于通过对从外部时钟信号产生的内部时钟信号进行分频而获得的第二时钟信号和通过划分第一时钟信号而获得的第三时钟信号。

3. 发明授权

US08134877B2 Semiconductor device having delay control circuit 有权
标题翻译：具有延迟控制电路的半导体装置
公开(公告)号：US08134877B2
公开(公告)日：2012-03-13
申请号：US12588200
申请日：2009-10-07
申请人： Kyoichi Nagata
发明人： Kyoichi Nagata
IPC分类号： G11C7/00
CPC分类号： G11C7/22 , G11C7/222 , G11C11/4076
摘要： A first delay circuit and a second delay circuit having different operation conditions from each other, a detection circuit that detects a difference in propagation speed of a pulse signal, which is simultaneously input to the first and second delay circuits, and a setting circuit that generates a selection signal based on a detection result from the detection circuit are provided. The selection signal is supplied to a delay control circuit that generates an operation timing signal by delaying a reference signal, of which a delay amount is controlled by the selection signal. With this arrangement, a necessity to set the delay amount of the delay control circuit with a large design margin can be eliminated considering PVT variation, and as a result, performance degradation can be prevented.
摘要翻译：具有彼此不同的工作条件的第一延迟电路和第二延迟电路，检测电路，其检测同时输入到第一和第二延迟电路的脉冲信号的传播速度差，以及产生提供了基于来自检测电路的检测结果的选择信号。选择信号被提供给延迟控制电路，该延迟控制电路通过延迟由选择信号控制延迟量的参考信号来产生操作定时信号。通过这种布置，考虑到PVT变化，可以消除设计具有大设计余量的延迟控制电路的延迟量的必要性，结果，可以防止性能下降。

4. 发明授权

US07875986B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US07875986B2
公开(公告)日：2011-01-25
申请号：US11822265
申请日：2007-07-03
申请人： Satoshi Isa , Mitsuaki Katagiri , Kyoichi Nagata , Seiji Narui
发明人： Satoshi Isa , Mitsuaki Katagiri , Kyoichi Nagata , Seiji Narui
IPC分类号： H01L29/40
CPC分类号： H01L23/50 , H01L23/49838 , H01L24/48 , H01L24/49 , H01L2224/05554 , H01L2224/48091 , H01L2224/48227 , H01L2224/49171 , H01L2924/00014 , H01L2924/01004 , H01L2924/01006 , H01L2924/01033 , H01L2924/01056 , H01L2924/01082 , H01L2924/014 , H01L2924/12041 , H01L2924/15311 , H01L2924/181 , H01L2924/30107 , H01L2924/00 , H01L2224/45099 , H01L2224/05599 , H01L2924/00012
摘要： Disclosed is a semiconductor memory device in which pads on a chip which are wire-bonded to lands for solder-balls of a package, respectively, are arranged on first and second sides of the chip facing to each other and are disposed on a third side of the chip as well. Four sets of the pads for data signals are respectively disposed on four regions obtained by dividing the first and second sides into the four regions. Pads for command/address signals are arranged on the third side, thereby increasing layout space for bond fingers for the data signals and achieving uniformity in wiring for data signals.
摘要翻译：公开了一种半导体存储器件，其中芯片上的焊盘分别焊接到封装的焊球的焊盘上，所述焊盘分别布置在芯片的彼此面对的第一和第二侧上，并且设置在第三侧的芯片以及。四组用于数据信号的焊盘分别设置在通过将第一和第二侧划分成四个区域而获得的四个区域上。用于命令/地址信号的板被布置在第三侧上，从而增加了用于数据信号的接合点的布局空间，并实现了数据信号的布线的均匀性。

5. 发明授权

US07436720B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US07436720B2
公开(公告)日：2008-10-14
申请号：US11605309
申请日：2006-11-29
申请人： Tomoko Nobutoki , Kyoichi Nagata
发明人： Tomoko Nobutoki , Kyoichi Nagata
IPC分类号： G11C7/00
CPC分类号： G11C7/18 , G11C7/02 , G11C7/1006 , G11C11/408 , G11C11/4096 , G11C11/4097
摘要： A semiconductor memory device includes plates accessed by different row addresses and a sense amplifier column between the adjacent plates. The sense amplifier column is a mixture of configurations, one in which one of the pair of bit lines is twisted, and another in which neither of the pair of bit lines is twisted. If an address analysis indicates that there is an access through an input/output wiring, input/output data is not inverted. If the address analysis indicates that there is an access through another input/output wiring and that it is an access to a plate, the input/output data is not inverted, while if it is an access to another plate, the input/output data is inverted.
摘要翻译：半导体存储器件包括通过不同行地址访问的板和相邻板之间的读出放大器柱。读出放大器列是配置的混合，其中一对位线中的一个被扭曲，另一个位置中的一对位线都不扭曲。如果地址分析表示通过输入/输出接线进行访问，则输入/输出数据不会反转。如果地址分析表明存在通过另一个输入/输出布线的访问，并且它是访问印版，则输入/输出数据不被反转，而如果访问另一个印版，输入/输出数据是倒置的

6. 发明申请

US20080001628A1 Level conversion circuit 审中-公开
标题翻译：电平转换电路
公开(公告)号：US20080001628A1
公开(公告)日：2008-01-03
申请号：US11808045
申请日：2007-06-06
申请人： Kyoichi Nagata
发明人： Kyoichi Nagata
IPC分类号： H03K19/0175
CPC分类号： H03K19/00323 , H03K19/018521
摘要： A level conversion circuit includes an input buffer receiving an external signal, cascade-connected inverter circuits arranged in rear of the input buffer, and a switching circuit supplying an internal power supply potential to a power supply terminal of the inverter circuit while an input signal input to the inverter circuit changes from low level to high level, and supplying an external power supply potential to the power supply terminal while the input signal changes from the high level to the low level. The difference between a time necessary for the input signal to exceed a threshold of one of the inverter circuits when the input signal changes from the low level to the high level and time necessary for the input signal to exceed the threshold of the inverter circuit when the input signal changes from the high level to the low level can be thereby reduced.
摘要翻译：电平转换电路包括接收外部信号的输入缓冲器，布置在输入缓冲器后部的级联连接的反相器电路和向逆变器电路的电源端子提供内部电源电位的开关电路，同时输入信号输入逆变器电路从低电平变化到高电平，并且在输入信号从高电平变为低电平时向电源端子提供外部电源电位。当输入信号从低电平变为高电平时，输入信号超过一个逆变器电路的阈值所需的时间与输入信号超过逆变器电路的阈值所需的时间之间的差异可以降低从高电平向低电平的输入信号变化。

7. 发明申请

US20070127301A1 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US20070127301A1
公开(公告)日：2007-06-07
申请号：US11605309
申请日：2006-11-29
申请人： Tomoko Nobutoki , Kyoichi Nagata
发明人： Tomoko Nobutoki , Kyoichi Nagata
IPC分类号： G11C7/00
CPC分类号： G11C7/18 , G11C7/02 , G11C7/1006 , G11C11/408 , G11C11/4096 , G11C11/4097
摘要： A semiconductor memory device includes plates accessed by different row addresses and a sense amplifier column between the adjacent plates. The sense amplifier column is a mixture of configurations, one in which one of the pair of bit lines is twisted, and another in which neither of the pair of bit lines is twisted. If an address analysis indicates that there is an access through an input/output wiring, input/output data is not inverted. If the address analysis indicates that there is an access through another input/output wiring and that it is an access to a plate, the input/output data is not inverted, while if it is an access to another plate, the input/output data is inverted.
摘要翻译：半导体存储器件包括通过不同行地址访问的板和相邻板之间的读出放大器柱。读出放大器列是配置的混合，其中一对位线中的一个被扭曲，另一个位置中的一对位线都不扭曲。如果地址分析表示通过输入/输出接线进行访问，则输入/输出数据不会反转。如果地址分析表明存在通过另一个输入/输出布线的访问，并且它是访问印版，则输入/输出数据不被反转，而如果访问另一个印版，输入/输出数据是倒置的

8. 发明授权

US5848006A Redundant semiconductor memory device using a single now address decoder for driving both sub-wordlines and redundant sub-wordlines 失效
标题翻译：冗余半导体存储器件使用单行地址解码器来驱动子字线和冗余子字线
公开(公告)号：US5848006A
公开(公告)日：1998-12-08
申请号：US753945
申请日：1996-12-03
申请人： Kyoichi Nagata
发明人： Kyoichi Nagata
IPC分类号： G11C8/12 , G11C29/00 , G11C8/00
CPC分类号： G11C29/80 , G11C29/844 , G11C8/12
摘要： A drive circuit for a semiconductor memory device in which a plurality of memory cell arrays are driven by a divisional decode system, includes a single, row address decoder including a plurality of address latch circuits for holding an address signal for normal operation via a first logic gate unit, and a plurality of normal/redundancy switching circuits for inputting therein held data, and an address signal for redundancy purposes, and for switching the input signal in response to a judging signal for redundancy purposes. The outputs of the switching circuits are activated through a second logic gate unit into which a row address enable signal is inputted. Thus, a driver selection signal during normal operation and a driver selection signal during a redundancy operation are commonly used. As a result, a total number of wiring lines and the number of driver circuits, as well as the chip area, are reduced.
摘要翻译：一种用于半导体存储器件的驱动电路，其中多个存储单元阵列由分割解码系统驱动，包括单个行地址解码器，其包括多个地址锁存电路，用于通过第一逻辑保持用于正常操作的地址信号门单元，以及用于在其中输入保持数据的多个正常/冗余切换电路和用于冗余目的的地址信号，并且为了冗余目的，响应于判断信号切换输入信号。开关电路的输出通过输入行地址使能信号的第二逻辑门单元激活。因此，通常使用在正常操作期间的驱动器选择信号和冗余操作期间的驱动器选择信号。结果，总线数和驱动电路的数量以及芯片面积都减少了。

9. 发明申请

US20100149894A1 Semiconductor memory device that can relief defective address 有权
标题翻译：可以缓解缺陷地址的半导体存储器件
公开(公告)号：US20100149894A1
公开(公告)日：2010-06-17
申请号：US12654202
申请日：2009-12-14
申请人： Noriaki Mochida , Kyoichi Nagata
发明人： Noriaki Mochida , Kyoichi Nagata
IPC分类号： G11C29/00 , G11C7/06 , G11C8/00
CPC分类号： G11C11/4076 , G11C11/4091 , G11C29/84
摘要： To comprise a memory cell array, a read amplifier that is provided outside the memory cell array and amplifies data read from the memory cell array, a write amplifier that is provided outside the memory cell array and amplifies data to be written in the memory cell array, and a relief storage cell that is provided outside the memory cell array and connected to an input terminal of the read amplifier and an output terminal of the write amplifier via a switch. With this configuration, a timing of operating a main amplifier and the relief storage cell does not need to be changed depending on a position of a memory block. Further, the number of components required for connecting to the relief storage cell can be minimized.
摘要翻译：为了构成存储单元阵列，设置在存储单元阵列的外部并放大从存储单元阵列读出的数据的读取放大器，设置在存储单元阵列外部的写放大器，并放大要写入存储单元阵列的数据以及设置在存储单元阵列外部并经由开关连接到读取放大器的输入端子和写入放大器的输出端子的释放存储单元。利用这种配置，根据存储块的位置，不需要改变操作主放大器和浮雕存储单元的定时。此外，可以使连接到浮雕存储单元所需的部件的数量最小化。

10. 发明授权

US07576566B2 Level-conversion circuit 有权
标题翻译：电平转换电路
公开(公告)号：US07576566B2
公开(公告)日：2009-08-18
申请号：US11850748
申请日：2007-09-06
申请人： Kyoichi Nagata
发明人： Kyoichi Nagata
IPC分类号： H03K19/0175
CPC分类号： H03K19/018521 , H03K19/0013
摘要： An independent control signal is transmitted to each of a driver control unit and an output transistor, so as to prevent the driver control unit and the output transistor from being made to operate at the same time and reduce through-current flows. Since the transistor ratio can be selected easily, the degree of designing flexibility increases and the speed enhancement is achieved.
摘要翻译：将独立的控制信号发送到驱动器控制单元和输出晶体管中的每一个，以防止驱动器控制单元和输出晶体管同时工作并减少直流电流。由于可以容易地选择晶体管比例，所以设计灵活性的程度增加并且实现了速度提高。

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