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1. 发明授权

US08358535B2 Semiconductor device including sub word line driver 有权
标题翻译：半导体器件包括子字线驱动器
公开(公告)号：US08358535B2
公开(公告)日：2013-01-22
申请号：US12911368
申请日：2010-10-25
申请人： Kyo-suk Chae , Satoru Yamada , Hyuk-joon Kwon , Won-kyung Park , Hyoung-ho Ko
发明人： Kyo-suk Chae , Satoru Yamada , Hyuk-joon Kwon , Won-kyung Park , Hyoung-ho Ko
IPC分类号： G11C11/34
CPC分类号： G11C8/14
摘要： A semiconductor device includes a sub word line driver. A first sub word line and a second sub word line transmit an operation signal to a memory cell. A main word line optionally sends the operation signal to the first sub word line and the second sub word line. A switching transistor is disposed between the first sub word line and the second sub word line. A gate of the switching transistor is connected the main word line.
摘要翻译：半导体器件包括子字线驱动器。第一子字线和第二子字线将操作信号发送到存储器单元。主字线可选地将操作信号发送到第一子字线和第二子字线。开关晶体管设置在第一子字线和第二子字线之间。开关晶体管的栅极连接主字线。

2. 发明申请

US20110170344A1 SEMICONDUCTOR DEVICE INCLUDING SUB WORD LINE DRIVER 有权
标题翻译：包括子字线驱动器的半导体器件
公开(公告)号：US20110170344A1
公开(公告)日：2011-07-14
申请号：US12911368
申请日：2010-10-25
申请人： KYO-SUK CHAE , Satoru Yamada , Hyuk-joon Kwon , Won-kyung Park , Hyoung-ho Ko
发明人： KYO-SUK CHAE , Satoru Yamada , Hyuk-joon Kwon , Won-kyung Park , Hyoung-ho Ko
IPC分类号： G11C11/34
CPC分类号： G11C8/14
摘要： A semiconductor device includes a sub word line driver. A first sub word line and a second sub word line transmit an operation signal to a memory cell. A main word line optionally sends the operation signal to the first sub word line and the second sub word line. A switching transistor is disposed between the first sub word line and the second sub word line. A gate of the switching transistor is connected the main word line.
摘要翻译：半导体器件包括子字线驱动器。第一子字线和第二子字线将操作信号发送到存储器单元。主字线可选地将操作信号发送到第一子字线和第二子字线。开关晶体管设置在第一子字线和第二子字线之间。开关晶体管的栅极连接主字线。

3. 发明申请

US20050030798A1 Semiconductor device and method for controlling the same 有权
标题翻译：半导体装置及其控制方法
公开(公告)号：US20050030798A1
公开(公告)日：2005-02-10
申请号：US10828454
申请日：2004-04-20
申请人： Jong-hyoung Lim , Hyuk-joon Kwon , Hyun-kyu Lee
发明人： Jong-hyoung Lim , Hyuk-joon Kwon , Hyun-kyu Lee
IPC分类号： G11C11/40 , G11C11/4076 , G11C11/4096 , G11C7/00
CPC分类号： G11C11/4076 , G11C11/4096 , G11C2207/002 , G11C2207/229
摘要： Disclosed herein are a semiconductor method and device which are capable of reducing data write errors by rewriting last write data during a write recovery time (tWR). The semiconductor device comprises a memory cell array consisting of a plurality of repetitive cell units; a bit line amplifier for amplifying a voltage difference between a bit line voltage and a complementary bit line voltage of the memory cell array; switching devices activated by a column selection line signal for electrically connecting a data line and a complementary data line to the bit line and the complementary bit line, respectively; and a write driver for supplying a write data voltage to the data line and the complementary data line, wherein the column selection line signal is generated during a write recovery time. The method for controlling the semiconductor device including a memory cell array having a plurality of repetitive cell units, a bit line amplifier for amplifying a voltage difference between a bit line voltage and a complementary bit line voltage of the memory cell array, switching devices activated by a column selection line signal for electrically connecting a data line and a complementary data line to the bit line and the complementary bit line, respectively, and a write driver for supplying a write data voltage to the data line and the complementary data line, comprises the steps of: writing data voltage into the memory cell array; and generating the column selection line signal during a write recovery time.
摘要翻译：这里公开了一种半导体方法和装置，其能够通过在写入恢复时间（tWR）期间重写最后写入数据来减少数据写入错误。半导体器件包括由多个重复单元单元组成的存储单元阵列; 位线放大器，用于放大存储单元阵列的位线电压和互补位线电压之间的电压差; 由列选择线信号激活的开关装置，用于将数据线和互补数据线分别电连接到位线和互补位线; 以及用于向数据线和互补数据线提供写数据电压的写驱动器，其中在写恢复时间期间产生列选择线信号。用于控制包括具有多个重复单元单元的存储单元阵列的半导体器件的方法，用于放大位线电压和存储单元阵列的互补位线电压之间的电压差的位线放大器，由用于将数据线和互补数据线分别电连接到位线和互补位线的列选择线信号和用于向数据线和互补数据线提供写数据电压的写驱动器，包括：步骤：将数据电压写入存储单元阵列; 以及在写恢复时间期间产生列选择线信号。

4. 发明授权

US08194486B2 Semiconductor memory devices having bit lines 有权
标题翻译：具有位线的半导体存储器件
公开(公告)号：US08194486B2
公开(公告)日：2012-06-05
申请号：US12591623
申请日：2009-11-25
申请人： Hyun-chul Yoon , Seong-jin Jang , Dong-hak Shin , Soo-hwan Kim , Hyuk-joon Kwon , Jong-min Oh
发明人： Hyun-chul Yoon , Seong-jin Jang , Dong-hak Shin , Soo-hwan Kim , Hyuk-joon Kwon , Jong-min Oh
IPC分类号： G11C7/06 , G11C7/08 , G11C5/06 , G11C7/02 , G11C11/4091 , G11C11/4097 , G11C11/4099
CPC分类号： G11C11/4091 , G11C7/065 , G11C7/12 , G11C11/4094 , G11C2207/005
摘要： A semiconductor device includes a bit line connected to a plurality of memory cells in a memory block and a sense amplifier having a first node connected to the bit line and a second node, which is not connected to any bit line. The second node has a capacitive load less than that of the bit line. The sense amplifier amplifies a first data using a voltage difference between the first node and the second node caused by a charge sharing operation, and a second data using a capacitive mismatch between the first node and the second node.
摘要翻译：半导体器件包括连接到存储器块中的多个存储器单元的位线和具有连接到位线的第一节点的读出放大器和不连接到任何位线的第二节点。第二节点的电容负载小于位线的容性负载。感测放大器使用由电荷共享操作引起的第一节点和第二节点之间的电压差放大第一数据，以及使用第一节点和第二节点之间的电容性失配来放大第二数据。

5. 发明授权

US07054204B2 Semiconductor device and method for controlling the same 有权
标题翻译：半导体装置及其控制方法
公开(公告)号：US07054204B2
公开(公告)日：2006-05-30
申请号：US10828454
申请日：2004-04-20
申请人： Jong-hyoung Lim , Hyuk-joon Kwon , Hyun-kyu Lee
发明人： Jong-hyoung Lim , Hyuk-joon Kwon , Hyun-kyu Lee
IPC分类号： G11C7/00 , G11C8/00
CPC分类号： G11C11/4076 , G11C11/4096 , G11C2207/002 , G11C2207/229
摘要： Disclosed herein are a semiconductor method and device which are capable of reducing data write errors by rewriting last write data during a write recovery time (tWR). The semiconductor device comprises a memory cell array consisting of a plurality of repetitive cell units; a bit line amplifier for amplifying a voltage difference between a bit line voltage and a complementary bit line voltage of the memory cell array; switching devices activated by a column selection line signal for electrically connecting a data line and a complementary data line to the bit line and the complementary bit line, respectively; and a write driver for supplying a write data voltage to the data line and the complementary data line, wherein the column selection line signal is generated during a write recovery time. The method for controlling the semiconductor device including a memory cell array having a plurality of repetitive cell units, a bit line amplifier for amplifying a voltage difference between a bit line voltage and a complementary bit line voltage of the memory cell array, switching devices activated by a column selection line signal for electrically connecting a data line and a complementary data line to the bit line and the complementary bit line, respectively, and a write driver for supplying a write data voltage to the data line and the complementary data line, comprises the steps of: writing data voltage into the memory cell array; and generating the column selection line signal during a write recovery time.
摘要翻译：这里公开了一种半导体方法和装置，其能够通过在写入恢复时间（tWR）期间重写最后写入数据来减少数据写入错误。半导体器件包括由多个重复单元单元组成的存储单元阵列; 位线放大器，用于放大存储单元阵列的位线电压和互补位线电压之间的电压差; 由列选择线信号激活的开关装置，用于将数据线和互补数据线分别电连接到位线和互补位线; 以及用于向数据线和互补数据线提供写数据电压的写驱动器，其中在写恢复时间期间产生列选择线信号。用于控制包括具有多个重复单元单元的存储单元阵列的半导体器件的方法，用于放大位线电压和存储单元阵列的互补位线电压之间的电压差的位线放大器，由用于将数据线和互补数据线分别电连接到位线和互补位线的列选择线信号和用于向数据线和互补数据线提供写数据电压的写驱动器，包括：步骤：将数据电压写入存储单元阵列; 以及在写恢复时间期间产生列选择线信号。

6. 发明授权

US07808804B2 Power line layout 有权
标题翻译：电源线布局
公开(公告)号：US07808804B2
公开(公告)日：2010-10-05
申请号：US11979868
申请日：2007-11-09
申请人： Hyuk-joon Kwon
发明人： Hyuk-joon Kwon
IPC分类号： G11C5/02
CPC分类号： G11C5/063
摘要： A power line layout for a semiconductor device includes a memory cell region, a plurality of wordline enable signal lines in the memory cell region, a plurality of first power lines arranged between the wordline enable signal lines in the memory cell region, and a plurality of second power lines arranged perpendicular to the first power lines in the memory cell region to form a mesh arrangement of first and second power lines.
摘要翻译：半导体器件的电源线布局包括存储单元区域，存储单元区域中的多个字线使能信号线，布置在存储单元区域中的字线使能信号线之间的多个第一电力线，以及多个与存储单元区域中的第一电力线垂直布置的第二电力线，以形成第一和第二电力线的网格布置。

7. 发明申请

US20100128514A1 Semiconductor memory devices having bit lines 有权
标题翻译：具有位线的半导体存储器件
公开(公告)号：US20100128514A1
公开(公告)日：2010-05-27
申请号：US12591623
申请日：2009-11-25
申请人： Hyun-chul Yoon , Seong-jin Jang , Dong-hak Shin , Soo-hwan Kim , Hyuk-joon Kwon , Jong-min Oh
发明人： Hyun-chul Yoon , Seong-jin Jang , Dong-hak Shin , Soo-hwan Kim , Hyuk-joon Kwon , Jong-min Oh
IPC分类号： G11C7/06 , G11C11/24 , G11C7/00
CPC分类号： G11C11/4091 , G11C7/065 , G11C7/12 , G11C11/4094 , G11C2207/005
摘要： A semiconductor device includes a bit line connected to a plurality of memory cells in a memory block and a sense amplifier having a first node connected to the bit line and a second node, which is not connected to any bit line. The second node has a capacitive load less than that of the bit line. The sense amplifier amplifies a first data using a voltage difference between the first node and the second node caused by a charge sharing operation, and a second data using a capacitive mismatch between the first node and the second node.
摘要翻译：半导体器件包括连接到存储器块中的多个存储器单元的位线和具有连接到位线的第一节点的读出放大器和不连接到任何位线的第二节点。第二节点的电容负载小于位线的容性负载。感测放大器使用由电荷共享操作引起的第一节点和第二节点之间的电压差放大第一数据，以及使用第一节点和第二节点之间的电容性失配来放大第二数据。

8. 发明申请

US20080112203A1 Power line layout 有权
标题翻译：电源线布局
公开(公告)号：US20080112203A1
公开(公告)日：2008-05-15
申请号：US11979868
申请日：2007-11-09
申请人： Hyuk-joon Kwon
发明人： Hyuk-joon Kwon
IPC分类号： G11C5/06
CPC分类号： G11C5/063
摘要： A power line layout for a semiconductor device includes a memory cell region, a plurality of wordline enable signal lines in the memory cell region, a plurality of first power lines arranged between the wordline enable signal lines in the memory cell region, and a plurality of second power lines arranged perpendicular to the first power lines in the memory cell region to form a mesh arrangement of first and second power lines.
摘要翻译：半导体器件的电源线布局包括存储单元区域，存储单元区域中的多个字线使能信号线，布置在存储单元区域中的字线使能信号线之间的多个第一电力线，以及多个与存储单元区域中的第一电力线垂直布置的第二电力线，以形成第一和第二电力线的网格布置。

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