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1. 发明授权

US09418988B2 Gate electrode and gate contact plug layouts for integrated circuit field effect transistors 有权
标题翻译：用于集成电路场效应晶体管的栅电极和栅极接触插头布局
公开(公告)号：US09418988B2
公开(公告)日：2016-08-16
申请号：US14461202
申请日：2014-08-15
申请人： Kyo-Suk Chae , Satoru Yamada , Sang-Yeon Han , Young-Jin Choi , Wook-Je Kim
发明人： Kyo-Suk Chae , Satoru Yamada , Sang-Yeon Han , Young-Jin Choi , Wook-Je Kim
IPC分类号： H01L27/088 , H01L29/423 , H01L29/78
CPC分类号： H01L27/088 , H01L23/535 , H01L27/0207 , H01L29/0649 , H01L29/0847 , H01L29/42376 , H01L29/4238 , H01L29/4933 , H01L29/7833
摘要： A four transistor layout can include an isolation region that defines an active region, the active region extending along first and second different directions. A common source region of the four transistors extends from a center of the active region along both the first and second directions to define four quadrants of the active region that are outside the common source region. Four drain regions are provided, a respective one of which is in a respective one of the four quadrants and spaced apart from the common source region. Finally, four gate electrodes are provided, a respective one of which is in a respective one of the four quadrants between the common source region and a respective one of the four drain regions. A respective gate electrode includes a vertex and first and second extending portions, the first extending portions extending from the vertex along the first direction and the second extending portions extending from the vertex along the second direction.
摘要翻译：四晶体管布局可以包括限定有源区域的隔离区域，有源区域沿第一和第二不同方向延伸。四个晶体管的共同源极区域从有源区域的中心沿着第一和第二方向延伸，以限定位于公共源极区域外的有源区域的四个象限。设置四个漏极区，其中的一个位于四个象限中的相应一个中并与公共源极区间隔开。最后，提供四个栅电极，其中的一个位于公共源极区域和四个漏极区域中的相应一个之间的四个象限中的相应一个中。相应的栅电极包括顶点和第一和第二延伸部分，第一延伸部分从顶点沿着第一方向延伸，第二延伸部分从顶点沿着第二方向延伸。

2. 发明授权

US08823113B2 Gate electrode and gate contact plug layouts for integrated circuit field effect transistors 有权
标题翻译：用于集成电路场效应晶体管的栅电极和栅极接触插头布局
公开(公告)号：US08823113B2
公开(公告)日：2014-09-02
申请号：US12984762
申请日：2011-01-05
申请人： Kyo-Suk Chae , Satoru Yamada , Sang-Yeon Han , Young-Jin Choi , Wook-Je Kim
发明人： Kyo-Suk Chae , Satoru Yamada , Sang-Yeon Han , Young-Jin Choi , Wook-Je Kim
IPC分类号： H01L27/088
CPC分类号： H01L27/088 , H01L23/535 , H01L27/0207 , H01L29/0649 , H01L29/0847 , H01L29/42376 , H01L29/4238 , H01L29/4933 , H01L29/7833
摘要： A four transistor layout can include an isolation region that defines an active region, the active region extending along first and second different directions. A common source region of the four transistors extends from a center of the active region along both the first and second directions to define four quadrants of the active region that are outside the common source region. Four drain regions are provided, a respective one of which is in a respective one of the four quadrants and spaced apart from the common source region. Finally, four gate electrodes are provided, a respective one of which is in a respective one of the four quadrants between the common source region and a respective one of the four drain regions. A respective gate electrode includes a vertex and first and second extending portions, the first extending portions extending from the vertex along the first direction and the second extending portions extending from the vertex along the second direction.
摘要翻译：四晶体管布局可以包括限定有源区域的隔离区域，有源区域沿第一和第二不同方向延伸。四个晶体管的共同源极区域从有源区域的中心沿着第一和第二方向延伸，以限定位于公共源极区域外的有源区域的四个象限。设置四个漏极区，其中的一个位于四个象限中的相应一个中并与公共源极区间隔开。最后，提供四个栅电极，其中的一个位于公共源极区域和四个漏极区域中的相应一个之间的四个象限中的相应一个中。相应的栅电极包括顶点和第一和第二延伸部分，第一延伸部分从顶点沿着第一方向延伸，第二延伸部分从顶点沿着第二方向延伸。

3. 发明申请

US20120001271A1 GATE ELECTRODE AND GATE CONTACT PLUG LAYOUTS FOR INTEGRATED CIRCUIT FIELD EFFECT TRANSISTORS 有权
标题翻译：门电极和门接触电路集成电路场效应晶体管
公开(公告)号：US20120001271A1
公开(公告)日：2012-01-05
申请号：US12984762
申请日：2011-01-05
申请人： Kyo-Suk Chae , Satoru Yamada , Sang-Yeon Han , Young-Jin Choi , Wook-Je Kim
发明人： Kyo-Suk Chae , Satoru Yamada , Sang-Yeon Han , Young-Jin Choi , Wook-Je Kim
IPC分类号： H01L27/088
CPC分类号： H01L27/088 , H01L23/535 , H01L27/0207 , H01L29/0649 , H01L29/0847 , H01L29/42376 , H01L29/4238 , H01L29/4933 , H01L29/7833
摘要： A four transistor layout can include an isolation region that defines an active region, the active region extending along first and second different directions. A common source region of the four transistors extends from a center of the active region along both the first and second directions to define four quadrants of the active region that are outside the common source region. Four drain regions are provided, a respective one of which is in a respective one of the four quadrants and spaced apart from the common source region. Finally, four gate electrodes are provided, a respective one of which is in a respective one of the four quadrants between the common source region and a respective one of the four drain regions. A respective gate electrode includes a vertex and first and second extending portions, the first extending portions extending from the vertex along the first direction and the second extending portions extending from the vertex along the second direction.
摘要翻译：四晶体管布局可以包括限定有源区域的隔离区域，有源区域沿第一和第二不同方向延伸。四个晶体管的共同源极区域从有源区域的中心沿着第一和第二方向延伸，以限定位于公共源极区域外的有源区域的四个象限。设置四个漏极区，其中的一个位于四个象限中的相应一个中并与公共源极区间隔开。最后，提供四个栅电极，其中的一个位于公共源极区域和四个漏极区域中的相应一个之间的四个象限中的相应一个中。相应的栅电极包括顶点和第一和第二延伸部分，第一延伸部分从顶点沿着第一方向延伸，第二延伸部分从顶点沿着第二方向延伸。

4. 发明申请

US20110076829A1 Semiconductor Devices and Methods of Forming the Same 审中-公开
标题翻译：半导体器件及其形成方法
公开(公告)号：US20110076829A1
公开(公告)日：2011-03-31
申请号：US12959559
申请日：2010-12-03
申请人： Wook-Je Kim , Satoru Yamada , Shin-Deuk Kim
发明人： Wook-Je Kim , Satoru Yamada , Shin-Deuk Kim
IPC分类号： H01L21/02
CPC分类号： H01L27/10894 , H01L27/105 , H01L27/10897
摘要： Provided are semiconductor devices and methods of forming the same. In the semiconductor devices and methods of forming the same, different insulating patterns are disposed around a cell gate pattern and a peripheral gate pattern to impose different heat budgets around the cell gate pattern and the peripheral gate pattern. For this purpose, a semiconductor substrate having a cell array region and a peripheral circuit region is prepared. First and second cell gate patterns are disposed in the cell array region. A peripheral gate pattern is disposed in the peripheral circuit region to be to adjacent to the second cell gate pattern. Buried insulating patterns are disposed around the first and second cell gate patterns. Planarization insulating patterns are disposed around the peripheral gate pattern.
摘要翻译：提供半导体器件及其形成方法。在半导体器件及其形成方法中，围绕单元栅极图案和外围栅极图案设置不同的绝缘图案，以在单元栅极图案和外围栅极图案周围施加不同的热量预算。为此，制备具有单元阵列区域和外围电路区域的半导体基板。第一和第二单元栅极图案设置在单元阵列区域中。周边电路图案设置在外围电路区域中以与第二单元栅极图案相邻。掩埋绝缘图案设置在第一和第二单元栅极图案周围。平面化绝缘图案设置在周边栅极图案周围。

5. 发明授权

US07868411B2 Semiconductor devices 有权
标题翻译：半导体器件
公开(公告)号：US07868411B2
公开(公告)日：2011-01-11
申请号：US12115745
申请日：2008-05-06
申请人： Wook-Je Kim , Satoru Yamada , Shin-Deuk Kim
发明人： Wook-Je Kim , Satoru Yamada , Shin-Deuk Kim
IPC分类号： H01L21/70
CPC分类号： H01L27/10894 , H01L27/105 , H01L27/10897
摘要： Provided are semiconductor devices and methods of forming the same. In the semiconductor devices and methods of forming the same, different insulating patterns are disposed around a cell gate pattern and a peripheral gate pattern to impose different heat budgets around the cell gate pattern and the peripheral gate pattern. For this purpose, a semiconductor substrate having a cell array region and a peripheral circuit region is prepared. First and second cell gate patterns are disposed in the cell array region. A peripheral gate pattern is disposed in the peripheral circuit region to be adjacent to the second cell gate pattern. Buried insulating patterns are disposed around the first and second cell gate patterns. Planarization insulating patterns are disposed around the peripheral gate pattern.
摘要翻译：提供半导体器件及其形成方法。在半导体器件及其形成方法中，围绕单元栅极图案和外围栅极图案设置不同的绝缘图案，以在单元栅极图案和外围栅极图案周围施加不同的热量预算。为此，制备具有单元阵列区域和外围电路区域的半导体基板。第一和第二单元栅极图案设置在单元阵列区域中。在周边电路区域设置与第二单元栅极图案相邻的外围栅极图案。掩埋绝缘图案设置在第一和第二单元栅极图案周围。平面化绝缘图案设置在周边栅极图案周围。

6. 发明申请

US20080277710A1 SEMICONDUCTOR DEVICES AND METHODS OF FORMING THE SAME 有权
标题翻译：半导体器件及其形成方法
公开(公告)号：US20080277710A1
公开(公告)日：2008-11-13
申请号：US12115745
申请日：2008-05-06
申请人： Wook-Je Kim , Satoru Yamada , Shin-Deuk Kim
发明人： Wook-Je Kim , Satoru Yamada , Shin-Deuk Kim
IPC分类号： H01L29/94 , H01L21/20
CPC分类号： H01L27/10894 , H01L27/105 , H01L27/10897
摘要： Provided are semiconductor devices and methods of forming the same. In the semiconductor devices and methods of forming the same, different insulating patterns are disposed around a cell gate pattern and a peripheral gate pattern to impose different heat budgets around the cell gate pattern and the peripheral gate pattern. For this purpose, a semiconductor substrate having a cell array region and a peripheral circuit region is prepared. First and second cell gate patterns are disposed in the cell array region. A peripheral gate pattern is disposed in the peripheral circuit region to be adjacent to the second cell gate pattern. Buried insulating patterns are disposed around the first and second cell gate patterns. Planarization insulating patterns are disposed around the peripheral gate pattern.
摘要翻译：提供半导体器件及其形成方法。在半导体器件及其形成方法中，围绕单元栅极图案和外围栅极图案设置不同的绝缘图案，以在单元栅极图案和外围栅极图案周围施加不同的热量预算。为此，制备具有单元阵列区域和外围电路区域的半导体基板。第一和第二单元栅极图案设置在单元阵列区域中。在周边电路区域设置与第二单元栅极图案相邻的外围栅极图案。掩埋绝缘图案设置在第一和第二单元栅极图案周围。平面化绝缘图案设置在周边栅极图案周围。

7. 发明授权

US08431462B2 Methods of manufacturing semiconductor devices 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US08431462B2
公开(公告)日：2013-04-30
申请号：US13183630
申请日：2011-07-15
申请人： Kwan-Heum Lee , Soon-Wook Jung , Jung-Hyun Park , Wook-Je Kim , Jong-Sang Ban
发明人： Kwan-Heum Lee , Soon-Wook Jung , Jung-Hyun Park , Wook-Je Kim , Jong-Sang Ban
IPC分类号： H01L21/337 , H01L21/8238 , H01L21/336 , H01L27/12
CPC分类号： H01L21/823814 , H01L21/823864 , H01L29/7848
摘要： A method of manufacturing a semiconductor device includes forming a gate structure on a substrate; forming a sacrificial spacer may be formed on a sidewall of the gate substrate; implanting first impurities into portions of the substrate by a first ion implantation process using the gate structure and the sacrificial spacer as ion implantation masks to form source and drain regions; removing the sacrificial spacer; and implanting second impurities and carbon atoms into portions of the substrate by a second ion implantation process using the gate structure as an ion implantation mask to form source and drain extension regions and carbon doping regions, respectively.
摘要翻译：一种制造半导体器件的方法包括在衬底上形成栅极结构; 形成牺牲隔离物可以形成在栅极衬底的侧壁上; 通过使用栅极结构和牺牲隔离物作为离子注入掩模的第一离子注入工艺将第一杂质注入到衬底的部分中以形成源区和漏区; 去除牺牲隔离物; 以及通过使用所述栅极结构作为离子注入掩模的第二离子注入工艺将第二杂质和碳原子注入到所述衬底的部分中，以分别形成源极和漏极延伸区域和碳掺杂区域。

8. 发明申请

US20050042832A1 Method of fabricating transistor of DRAM semiconductor device 有权
标题翻译：制造DRAM半导体器件晶体管的方法
公开(公告)号：US20050042832A1
公开(公告)日：2005-02-24
申请号：US10922055
申请日：2004-08-18
申请人： Yong-Chul Oh , Wook-Je Kim , Nak-Jin Son , Se-Myeong Jang , Gyo-Young Jin
发明人： Yong-Chul Oh , Wook-Je Kim , Nak-Jin Son , Se-Myeong Jang , Gyo-Young Jin
IPC分类号： H01L29/78 , H01L21/28 , H01L21/8238 , H01L21/8242 , H01L29/51 , H01L21/3205 , H01L29/76 , H01L31/062
CPC分类号： H01L21/823878 , H01L21/28185 , H01L21/28202 , H01L21/823807 , H01L21/823842 , H01L21/823857 , H01L27/10873 , H01L27/10894 , H01L29/513 , H01L29/518
摘要： Embodiments prevent or substantially reduce diffusion of a P-type impurity into a channel region in a PMOS transistor having a dual gate. Some embodiments include forming a device isolation film on a semiconductor substrate, forming a channel impurity region in an active region of the semiconductor substrate, and forming a gate insulation layer including a silicon oxide layer and a silicon oxide nitride layer on the semiconductor substrate. Also, the embodiments can include forming a polysilicon layer containing an N-type impurity on the gate insulation layer, and forming a gate electrode by selectively ion-implanting a P-type impurity into the polysilicon layer formed in a PMOS transistor region of the circuit region. The embodiments further include forming a conductive metal layer and a gate upper insulation layer on the gate electrode, and forming a gate stack in a gate region.
摘要翻译：实施例防止或基本上减少P型杂质扩散到具有双栅极的PMOS晶体管中的沟道区域中。一些实施例包括在半导体衬底上形成器件隔离膜，在半导体衬底的有源区中形成沟道杂质区，并在半导体衬底上形成包括氧化硅层和氧化硅氮化物层的栅极绝缘层。此外，实施例可以包括在栅极绝缘层上形成含有N型杂质的多晶硅层，并且通过选择性地将P型杂质离子注入形成在电路的PMOS晶体管区域中的多晶硅层中来形成栅电极地区。实施例还包括在栅电极上形成导电金属层和栅极上绝缘层，以及在栅极区域中形成栅叠层。

9. 发明授权

US09401428B2 Semiconductor devices including gate pattern, multi-channel active pattern and diffusion layer 有权
标题翻译：半导体器件包括栅极图案，多通道有源图案和扩散层
公开(公告)号：US09401428B2
公开(公告)日：2016-07-26
申请号：US13795778
申请日：2013-03-12
申请人： Kyung-In Choi , Gyeom Kim , Hong-Sik Yoon , Bon-Young Koo , Wook-Je Kim
发明人： Kyung-In Choi , Gyeom Kim , Hong-Sik Yoon , Bon-Young Koo , Wook-Je Kim
IPC分类号： H01L29/76 , H01L29/78 , H01L21/8234 , H01L21/8238 , H01L29/66
CPC分类号： H01L29/66795 , H01L21/823431 , H01L21/823821 , H01L29/66545 , H01L29/785 , H01L2924/13067
摘要： A semiconductor device includes a gate pattern on a substrate, a multi-channel active pattern under the gate pattern to cross the gate pattern and having a first region not overlapping the gate pattern and a second region overlapping the gate pattern, a diffusion layer in the multi-channel active pattern along the outer periphery of the first region and including an impurity having a concentration, and a liner on the multi-channel active pattern, the liner extending on lateral surfaces of the first region and not extending on a top surface of the first region. Related fabrication methods are also described.
摘要翻译：半导体器件包括衬底上的栅极图案，栅极图案下方的跨越栅极图案的多通道有源图案，并且具有不与栅极图案重叠的第一区域和与栅极图案重叠的第二区域，多通道活性图案沿着第一区域的外周边并且包括具有浓度的杂质和多通道活性图案上的衬垫，衬垫在第一区域的侧表面上延伸并且不在第一区域的顶表面上延伸第一个地区。还描述了相关的制造方法。

10. 发明授权

US06838341B2 Method for fabricating semiconductor device with self-aligned storage node 失效
标题翻译：用于制造具有自对准存储节点的半导体器件的方法
公开(公告)号：US06838341B2
公开(公告)日：2005-01-04
申请号：US10688079
申请日：2003-10-16
申请人： Jae-Man Yoon , Yun-Jae Lee , Sang-Hyun Lee , Wook-Je Kim
发明人： Jae-Man Yoon , Yun-Jae Lee , Sang-Hyun Lee , Wook-Je Kim
IPC分类号： H01L21/02 , H01L21/336 , H01L21/60 , H01L21/768 , H01L21/8242 , H01L27/108
CPC分类号： H01L27/10814 , H01L21/76802 , H01L21/76897 , H01L27/10855 , H01L28/91
摘要： A method for fabricating a semiconductor device includes preparing a semiconductor substrate having a contact pad; forming a first insulating film having a storage node contact exposing the contact pad and having a stack structure of an upper interlayer insulating film, a bottom interlayer insulating film, and an etching stopper between the upper and bottom interlayer insulating layers that protrudes into the storage node contact; forming a first conductive film for a storage node on the substrate; forming a second insulating film where a portion of a surface corresponding to the storage node contact is recessed; forming an etching mask layer on the recessed portion of the second insulating film; etching the second insulating film using the etching mask layer; forming a second conductive film for a storage node on the substrate; etching the first and second conductive films to isolate nodes; and removing the etching mask layer, the second insulating film and the upper interlayer insulating film.

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