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1. 发明申请

US20180068742A1 DEVICE AND METHOD FOR REPAIRING MEMORY CELL AND MEMORY SYSTEM INCLUDING THE DEVICE 审中-公开
公开(公告)号：US20180068742A1
公开(公告)日：2018-03-08
申请号：US15795595
申请日：2017-10-27
申请人： Kyo-Min Sohn , Ho-Young Song , Sang-Joon Hwang , Cheol Kim , Dong-Hyun Sohn
发明人： Kyo-Min Sohn , Ho-Young Song , Sang-Joon Hwang , Cheol Kim , Dong-Hyun Sohn
IPC分类号： G11C29/44 , G11C17/16 , G11C11/4078 , G11C11/4094 , G11C11/4096 , G11C17/18 , G11C29/36 , G11C29/42 , G11C29/00
CPC分类号： G11C29/44 , G01R31/3187 , G06F11/2053 , G06F11/27 , G11B20/1816 , G11C5/04 , G11C8/06 , G11C8/10 , G11C11/40 , G11C11/4078 , G11C11/4094 , G11C11/4096 , G11C17/16 , G11C17/18 , G11C29/027 , G11C29/36 , G11C29/42 , G11C29/4401 , G11C29/56 , G11C29/56008 , G11C29/78 , G11C29/785 , G11C2029/4402 , G11C2029/5606
摘要： Provided are a method and an apparatus for repairing a memory cell in a memory test system. A test device detects a fail address by testing a memory device according to a test command, and temporarily stores the fail address in a fail address memory (FAM). The fail address is transmitted to the memory device according to a fail address transmission mode, is temporarily stored in a temporary fail address storage of the memory device, and is then stored in an anti-fuse array, which is a non-volatile storage device. To secure the reliability of data, stored data can be read to verify the data and a verification result can be transmitted in series or in parallel to the test device.

2. 发明授权

US09087613B2 Device and method for repairing memory cell and memory system including the device 有权
标题翻译：包括设备在内的修复存储单元和存储器系统的装置和方法
公开(公告)号：US09087613B2
公开(公告)日：2015-07-21
申请号：US13753165
申请日：2013-01-29
申请人： Kyo-Min Sohn , Ho-Young Song , Sang-Joon Hwang , Cheol Kim , Dong-Hyun Sohn
发明人： Kyo-Min Sohn , Ho-Young Song , Sang-Joon Hwang , Cheol Kim , Dong-Hyun Sohn
IPC分类号： G11C29/00 , G11C29/44 , G06F11/27 , G06F11/20 , G11C29/56 , G01R31/3187 , G11B20/18 , G11C5/04 , G11C11/40 , G11C17/16 , G11C17/18 , G11C29/02
CPC分类号： G11C29/4401 , G01R31/3187 , G06F11/2053 , G06F11/27 , G11B20/1816 , G11C5/04 , G11C8/06 , G11C8/10 , G11C11/40 , G11C11/4078 , G11C11/4094 , G11C11/4096 , G11C17/16 , G11C17/18 , G11C29/027 , G11C29/36 , G11C29/42 , G11C29/44 , G11C29/56 , G11C29/56008 , G11C29/78 , G11C29/785 , G11C2029/4402 , G11C2029/5606
摘要： Provided are a method and an apparatus for repairing a memory cell in a memory test system. A test device detects a fail address by testing a memory device according to a test command, and temporarily stores the fail address in a fail address memory (FAM). The fail address is transmitted to the memory device according to a fail address transmission mode, is temporarily stored in a temporary fail address storage of the memory device, and is then stored in an anti-fuse array, which is a non-volatile storage device. To secure the reliability of data, stored data can be read to verify the data and a verification result can be transmitted in series or in parallel to the test device.
摘要翻译：提供了一种用于修复存储器测试系统中的存储单元的方法和装置。测试设备通过根据测试命令测试存储设备来检测故障地址，并将故障地址临时存储在故障地址存储器（FAM）中。故障地址根据故障地址传输模式发送到存储设备，被临时存储在存储器件的暂时失效地址存储器中，然后存储在作为非易失性存储设备的反熔丝阵列。为了确保数据的可靠性，可以读取存储的数据以验证数据，并且验证结果可以与测试设备串联或并行传输。

3. 发明申请

US20150243374A1 DEVICE AND METHOD FOR REPAIRING MEMORY CELL AND MEMORY SYSTEM INCLUDING THE DEVICE 有权
标题翻译：用于修复包含设备的存储器单元和存储器系统的装置和方法
公开(公告)号：US20150243374A1
公开(公告)日：2015-08-27
申请号：US14698219
申请日：2015-04-28
申请人： Kyo-Min Sohn , Ho-Young Song , Sang-Joon Hwang , Cheol Kim , Dong-Hyun Sohn
发明人： Kyo-Min Sohn , Ho-Young Song , Sang-Joon Hwang , Cheol Kim , Dong-Hyun Sohn
IPC分类号： G11C29/00 , G11C8/10 , G11C8/06 , G11C17/16 , G11C17/18
CPC分类号： G11C29/4401 , G01R31/3187 , G06F11/2053 , G06F11/27 , G11B20/1816 , G11C5/04 , G11C8/06 , G11C8/10 , G11C11/40 , G11C11/4078 , G11C11/4094 , G11C11/4096 , G11C17/16 , G11C17/18 , G11C29/027 , G11C29/36 , G11C29/42 , G11C29/44 , G11C29/56 , G11C29/56008 , G11C29/78 , G11C29/785 , G11C2029/4402 , G11C2029/5606
摘要： Provided are a method and an apparatus for repairing a memory cell in a memory test system. A test device detects a fail address by testing a memory device according to a test command, and temporarily stores the fail address in a fail address memory (FAM). The fail address is transmitted to the memory device according to a fail address transmission mode, is temporarily stored in a temporary fail address storage of the memory device, and is then stored in an anti-fuse array, which is a non-volatile storage device. To secure the reliability of data, stored data can be read to verify the data and a verification result can be transmitted in series or in parallel to the test device.
摘要翻译：提供了一种用于修复存储器测试系统中的存储单元的方法和装置。测试设备通过根据测试命令测试存储设备来检测故障地址，并将故障地址临时存储在故障地址存储器（FAM）中。故障地址根据故障地址传输模式发送到存储设备，被临时存储在存储器件的暂时失效地址存储器中，然后存储在作为非易失性存储设备的反熔丝阵列。为了确保数据的可靠性，可以读取存储的数据以验证数据，并且验证结果可以与测试设备串联或并行传输。

4. 发明申请

US20130227344A1 DEVICE AND METHOD FOR REPAIRING MEMORY CELL AND MEMORY SYSTEM INCLUDING THE DEVICE 有权
公开(公告)号：US20130227344A1
公开(公告)日：2013-08-29
申请号：US13753165
申请日：2013-01-29
申请人： Kyo-Min Sohn , Ho-Young Song , Sang-Joon Hwang , Cheol Kim , Dong-Hyun Sohn
发明人： Kyo-Min Sohn , Ho-Young Song , Sang-Joon Hwang , Cheol Kim , Dong-Hyun Sohn
IPC分类号： G06F11/27 , G06F11/20
CPC分类号： G11C29/4401 , G01R31/3187 , G06F11/2053 , G06F11/27 , G11B20/1816 , G11C5/04 , G11C8/06 , G11C8/10 , G11C11/40 , G11C11/4078 , G11C11/4094 , G11C11/4096 , G11C17/16 , G11C17/18 , G11C29/027 , G11C29/36 , G11C29/42 , G11C29/44 , G11C29/56 , G11C29/56008 , G11C29/78 , G11C29/785 , G11C2029/4402 , G11C2029/5606
摘要： Provided are a method and an apparatus for repairing a memory cell in a memory test system. A test device detects a fail address by testing a memory device according to a test command, and temporarily stores the fail address in a fail address memory (FAM). The fail address is transmitted to the memory device according to a fail address transmission mode, is temporarily stored in a temporary fail address storage of the memory device, and is then stored in an anti-fuse array, which is a non-volatile storage device. To secure the reliability of data, stored data can be read to verify the data and a verification result can be transmitted in series or in parallel to the test device.

5. 发明授权

US09336906B2 Semiconductor memory devices including redundancy memory cells 有权
标题翻译：包括冗余存储单元的半导体存储器件
公开(公告)号：US09336906B2
公开(公告)日：2016-05-10
申请号：US14503691
申请日：2014-10-01
申请人： Yun-Young Lee , Kyo-Min Sohn , Sang-Joon Hwang , Sung-Min Seo , Sang-Bo Lee , Nak-Won Heo
发明人： Yun-Young Lee , Kyo-Min Sohn , Sang-Joon Hwang , Sung-Min Seo , Sang-Bo Lee , Nak-Won Heo
IPC分类号： G11C7/00 , G11C29/00 , G11C11/406 , G11C17/16
CPC分类号： G11C11/40615 , G11C11/406 , G11C11/408 , G11C17/16 , G11C29/44 , G11C29/783 , G11C29/785 , G11C2029/4402
摘要： A semiconductor memory device includes a memory cell array, a repair control circuit and a refresh control circuit. The memory cell array includes a plurality of memory cells and a plurality of redundancy memory cells. The repair control circuit receives a repair command and performs a repair operation on a first defective memory cell among the plurality of memory cells during a repair mode. The semiconductor memory device may operate in a repair mode in response to the repair command. The refresh control circuit performs a refresh operation on non-defective ones of the plurality of memory cells during the repair mode.
摘要翻译：半导体存储器件包括存储单元阵列，修复控制电路和刷新控制电路。存储单元阵列包括多个存储单元和多个冗余存储单元。修复控制电路在修复模式期间接收修复命令并对多个存储单元中的第一有缺陷存储单元执行修复操作。半导体存储器件可以响应于修复命令在修复模式下操作。刷新控制电路在修复模式期间对多个存储单元中的无缺陷存储单元执行刷新操作。

6. 发明申请

US20150221361A1 Semiconductor Memory Devices Including Redundancy Memory Cells 有权
标题翻译：包括冗余存储器单元的半导体存储器件
公开(公告)号：US20150221361A1
公开(公告)日：2015-08-06
申请号：US14503691
申请日：2014-10-01
申请人： Yun-Young Lee , Kyo-Min Sohn , Sang-Joon Hwang , Sung-Min Seo , Sang-Bo Lee , Nak-Won Heo
发明人： Yun-Young Lee , Kyo-Min Sohn , Sang-Joon Hwang , Sung-Min Seo , Sang-Bo Lee , Nak-Won Heo
IPC分类号： G11C11/406 , G11C11/408 , G11C17/16
CPC分类号： G11C11/40615 , G11C11/406 , G11C11/408 , G11C17/16 , G11C29/44 , G11C29/783 , G11C29/785 , G11C2029/4402
摘要： A semiconductor memory device includes a memory cell array, a repair control circuit and a refresh control circuit. The memory cell array includes a plurality of memory cells and a plurality of redundancy memory cells. The repair control circuit receives a repair command and performs a repair operation on a first defective memory cell among the plurality of memory cells during a repair mode. The semiconductor memory device may operate in a repair mode in response to the repair command. The refresh control circuit performs a refresh operation on non-defective ones of the plurality of memory cells during the repair mode.
摘要翻译：半导体存储器件包括存储单元阵列，修复控制电路和刷新控制电路。存储单元阵列包括多个存储单元和多个冗余存储单元。修复控制电路在修复模式期间接收修复命令并对多个存储单元中的第一有缺陷存储单元执行修复操作。半导体存储器件可以响应于修复命令在修复模式下操作。刷新控制电路在修复模式期间对多个存储单元中的无缺陷存储单元执行刷新操作。

7. 发明授权

US06483770B2 Synchronous semiconductor memory device and method for operating same 有权
标题翻译：同步半导体存储器件及其操作方法
公开(公告)号：US06483770B2
公开(公告)日：2002-11-19
申请号：US09849289
申请日：2001-05-04
申请人： Yong-Hwan Noh , Kyo-Min Sohn
发明人： Yong-Hwan Noh , Kyo-Min Sohn
IPC分类号： G11C800
CPC分类号： G11C7/1039 , G11C7/1072
摘要： Disclosed is a semiconductor memory device comprising a pipeline structure having a sense amplifier responsive to a first enable signal; a data register responsive to a second enable signal for latching an output of said sense amplifier between said sense amplifier and a common data line; and a monitoring part to monitor said first and second enable signals and adapted to prevent overlapping between an enabling interval of said first enable signal and said second enable signal.
摘要翻译：公开了一种半导体存储器件，其包括具有响应于第一使能信号的读出放大器的流水线结构; 响应于第二使能信号的数据寄存器，用于锁存所述读出放大器与公共数据线之间的所述读出放大器的输出; 以及监视部分，用于监视所述第一和第二使能信号并适于防止所述第一使能信号的使能间隔和所述第二使能信号之间的重叠。

8. 发明授权

US06150873A Internal voltage converter for low operating voltage semiconductor memory 有权
标题翻译：用于低工作电压半导体存储器的内部电压转换器
公开(公告)号：US06150873A
公开(公告)日：2000-11-21
申请号：US288771
申请日：1999-04-08
申请人： Kyo-Min Sohn , Young-Ho Suh
发明人： Kyo-Min Sohn , Young-Ho Suh
IPC分类号： G11C11/413 , G05F1/46 , G05F1/56 , G11C11/407 , H01L27/07 , G05F3/02
CPC分类号： G05F1/465
摘要： The present invention provides an internal voltage converter that comprises a voltage down converter which receives an external voltage and provides an intermediate voltage that is stable and lower than the external voltage. The intermediate voltage is used to operate a clock signal generator and a timing controller that produces a timing signal. The regulator also includes a booster that receives the timing signal and the external voltage, and outputs a boosted voltage that is of a lower level than in the prior art. The regulator also includes a voltage source that receives the boosted voltage and the external voltage, and outputs the device's internal operating voltage for operating it.
摘要翻译：本发明提供一种内部电压转换器，其包括接收外部电压并提供稳定且低于外部电压的中间电压的降压转换器。中间电压用于操作产生定时信号的时钟信号发生器和定时控制器。调节器还包括接收定时信号和外部电压的升压器，并输出比现有技术低的升压电压。调节器还包括一个接收升压电压和外部电压的电压源，并输出器件的内部工作电压进行操作。

9. 发明授权

US07193903B2 Method of controlling an integrated circuit capable of simultaneously performing a data read operation and a data write operation 有权
标题翻译：控制能够同时执行数据读取操作和数据写入操作的集成电路的方法
公开(公告)号：US07193903B2
公开(公告)日：2007-03-20
申请号：US10811613
申请日：2004-03-29
申请人： Kyo-Min Sohn , Young-Ho Suh
发明人： Kyo-Min Sohn , Young-Ho Suh
IPC分类号： G11C7/10
CPC分类号： G11C8/16 , G11C7/22
摘要： A method of controlling an integrated circuit (IC) capable of simultaneously performing a data read operation and a data write operation is provided. The method comprises (a) receiving a write address, a read address, and write data, (b) determining, a memory block and a data memory block in which a data read operation and a data write operation are to be performed in response to the write address and the read address, (c) performing the data read operation or the data write operation in the data memory block according to the determination of step (b), and (d) performing the data read operation or the data write operation in the memory block according to the determination of step (b).
摘要翻译：提供一种控制能够同时执行数据读取操作和数据写入操作的集成电路（IC）的方法。该方法包括：（a）接收写入地址，读取地址和写入数据，（b）确定存储器块和数据存储器块，其中将响应于数据读取操作和数据写入操作执行数据读取操作和数据写入操作写入地址和读取地址，（c）根据步骤（b）的确定执行数据存储块中的数据读取操作或数据写入操作，以及（d）执行数据读取操作或数据写入操作根据步骤（b）的确定在存储器块中。

10. 发明授权

US06456551B2 Semiconductor memory device having prefetch operation mode and data transfer method for reducing the number of main data lines 有权
标题翻译：具有用于减少主数据线的数量的预取操作模式和数据传输方法的半导体存储器件
公开(公告)号：US06456551B2
公开(公告)日：2002-09-24
申请号：US09846156
申请日：2001-04-30
申请人： Kyo-Min Sohn , Yong-Hwan Noh
发明人： Kyo-Min Sohn , Yong-Hwan Noh
IPC分类号： G11C700
CPC分类号： G11C7/106 , G11C7/1048 , G11C7/1051 , G11C2207/002 , G11C2207/107
摘要： A synchronous semiconductor memory device includes a plurality of main data lines each coupled between a block sense amplifier array and a data output buffer. Each main data line prefetches a plurality of cell data segments from memory cells corresponding to an input/output port and transmits the cell data to the data output buffer. The memory device also includes a pass/latch part connected to one or more corresponding block sense amplifiers within a corresponding block sense amplifier array. The pass/latch part receives a plurality of cell data segments in parallel from the block sense amplifiers and transmits them in series to a corresponding main data line. This invention reduces a chip size and peak electric current of the semiconductor device by minimizing the number of main data lines required for prefetch operations.
摘要翻译：同步半导体存储器件包括多个主数据线，每个主数据线分别耦合在块读出放大器阵列和数据输出缓冲器之间。每个主数据线从对应于输入/输出端口的存储器单元中预取多个单元数据段，并将单元数据发送到数据输出缓冲器。存储器件还包括连接到相应的块读出放大器阵列内的一个或多个对应的块读出放大器的通过/锁存部分。通过/锁存部分从块读出放大器并行地接收多个单元数据段，并将它们串联发送到对应的主数据线。本发明通过最小化预取操作所需的主数据线的数量来减少半导体器件的芯片尺寸和峰值电流。

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