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1. 发明授权

US5905769A System and method for high-speed skew-insensitive multi-channel data transmission 失效
标题翻译：用于高速偏移多通道数据传输的系统和方法
公开(公告)号：US5905769A
公开(公告)日：1999-05-18
申请号：US646450
申请日：1996-05-07
申请人： Kyeongho Lee , Deog-Kyon Jeong
发明人： Kyeongho Lee , Deog-Kyon Jeong
IPC分类号： H04L7/00 , H04L7/033 , H04L7/04 , H04N7/083 , H04N7/52 , H04N21/2368 , H04N21/434 , H03D3/24
CPC分类号： H04N7/52 , H04L7/0337 , H04N21/4305 , H04N7/083 , H04L2007/045 , H04L7/0008
摘要： A method and apparatus is disclosed that receives a multi-channel digital serial encoded signal and converting it signal into a synchronized set of binary characters. A charge pump phase-locked loop receives a transmitted reference clock and derives a multi-phase clock from the reference clock. The multi-phase clock is used to control a plurality of multi-bit block assembly circuits. Each assembly circuit receives one channel of the digital signal and produces a multi-bit block or character. The multi-bit block assembly circuit includes an oversampler, a digital phase-locked loop and a byte synchronizer. The oversampler oversamples the received digital signal under control of the multiphase clock and produces a sequence of oversampled binary data. The digital phase-locked loop receives the oversampled data and selects samples from it depending on the skew characteristics of the sample. The byte synchronizer assembles a sequence of selected bits into a bit block, or character. An interchannel synchronizer receives as input the characters produced by each of the multi-bit block assembly circuits, and selectively delays output of the received characters in order to synchronize the characters of each channel with one another.
摘要翻译：公开了一种接收多通道数字串行编码信号并将其转换成同步的二进制字符集的方法和装置。电荷泵锁相环接收传输的参考时钟并从参考时钟导出多相时钟。多相时钟用于控制多个多位块组合电路。每个汇编电路接收数字信号的一个通道并产生多位块或字符。多比特块组合电路包括过采样器，数字锁相环和字节同步器。过采样器在多相时钟的控制下对接收到的数字信号进行过采样，并产生过采样二进制数据序列。数字锁相环接收过采样数据，并根据样本的偏斜特性从中选择样本。字节同步器将选定位的序列组合成位块或字符。通道间同步器接收由多位块组合电路中的每一个产生的字符作为输入，并且选择性地延迟所接收字符的输出，以便使每个通道的字符彼此同步。

2. 发明授权

US5825824A DC-balanced and transition-controlled encoding method and apparatus 失效
标题翻译：直流平衡和过渡控制编码方法和装置
公开(公告)号：US5825824A
公开(公告)日：1998-10-20
申请号：US622810
申请日：1996-03-27
申请人： Kyeongho Lee , Deog-Kyon Jeong
发明人： Kyeongho Lee , Deog-Kyon Jeong
IPC分类号： H03M7/14 , H03M5/14 , H04L7/00 , H04L7/04 , H04L25/03 , H04L25/08 , H04L25/49 , H04N7/083 , H04N7/52 , H04N21/2368 , H04N21/434 , H04L25/34 , H03M5/00 , H04J3/24
CPC分类号： H04L25/085 , H04L25/03866 , H04L25/4915 , H04N21/2368 , H04N21/4341 , H04N7/083 , H04N7/52 , H04L2007/045 , H04L7/0008
摘要： A method and apparatus for producing a transition-controlled, DC-balanced sequence of characters from an input sequence of data bytes. The bits in each of the data bytes are selectively complemented in accordance with the number of logical `1` signals in each data byte in order to produce selectively complemented data blocks. A cumulative disparity is then determined between the logical values of different type included within ones of the selectively complemented data blocks previously encoded into characters. In addition, a current disparity in a candidate character associated with a current one of the selectively complemented data blocks being encoded is also determined. The candidate character is assigned to the current one of the selectively complemented data blocks if the current disparity is of a polarity opposite to a first polarity of the cumulative disparity. Alternately, the complement of the candidate character is assigned to the current one of the selectively complemented data blocks if the current disparity is of the first polarity. In a high-transition mode of operation, the bits within data blocks including fewer than a minimum number of logical `1` signals are selectively complemented so that each such selectively complemented data block includes in excess of the minimum number of logical transitions. In a low-transition mode of operation, the bits within data blocks having more than a predefined number of logical `1` signals are selectively complemented so that each such selectively complemented data block includes less than the maximum number of logical transitions.
摘要翻译：一种用于从数据字节的输入序列产生转换控制的直流平衡字符序列的方法和装置。每个数据字节中的位根据每个数据字节中的逻辑“1”信号的数目选择性地补充，以便产生选择性补充的数据块。然后在包括在先前编码为字符的选择性补充的数据块中的不同类型的逻辑值之前确定累积差异。此外，还确定与被编码的选择性补充的数据块中的当前一个相关联的候选字符中的当前差异。如果当前视差与累积视差的第一极性相反的极性，则候选字符被分配给选择性补充的数据块中的当前一个。或者，如果当前视差是第一极性，则候选字符的补码被分配给选择性补充的数据块中的当前一个。在高转换操作模式中，选择性地补充包括少于最小数量的逻辑“1”信号的数据块内的位，使得每个这样的选择性补充的数据块包括超过最小数量的逻辑转换。在低转换操作模式中，选择性地补充具有超过预定数量的逻辑“1”信号的数据块内的位，使得每个这样的选择性补充的数据块包括小于逻辑转换的最大数量。

3. 发明授权

US6026124A Transition-controlled digital encoding and signal transmission system 失效
公开(公告)号：US6026124A
公开(公告)日：2000-02-15
申请号：US97021
申请日：1998-06-12
申请人： Kyeongho Lee , Deog-Kyon Jeong
发明人： Kyeongho Lee , Deog-Kyon Jeong
IPC分类号： H03M7/14 , H03M5/14 , H04L7/00 , H04L7/04 , H04L25/03 , H04L25/08 , H04L25/49 , H04N7/083 , H04N7/52 , H04N21/2368 , H04N21/434 , H04L25/34 , H03M13/00 , H04J3/24
CPC分类号： H04L25/085 , H04L25/03866 , H04L25/4915 , H04N21/2368 , H04N21/4341 , H04N7/083 , H04N7/52 , H04L2007/045 , H04L7/0008
摘要： A method and apparatus for producing a transition-controlled, DC-balanced sequence of characters from an input sequence of data bytes is disclosed herein. The bits in each of the data bytes are selectively complemented in accordance with the number of logical `1` signals in each data byte in order to produce selectively complemented data blocks. A cumulative disparity is then determined between the logical values of different type included within ones of the selectively complemented data blocks previously encoded into characters. In addition, a current disparity in a candidate character associated with a current one of the selectively complemented data blocks being encoded is also determined. The candidate character is assigned to the current one of the selectively complemented data blocks if the current disparity is of a polarity opposite to a first polarity of the cumulative disparity. Alternately, the complement of the candidate character is assigned to the current one of the selectively complemented data blocks if the current disparity is of the first polarity. In a high-transition mode of operation, the bits within data blocks including fewer than a minimum number of logical `1` signals are selectively complemented so that each such selectively complemented data block includes in excess of the minimum number of logical transitions. In a low-transition mode of operation, the bits within data blocks having more than a predefined number of logical `1` signals are selectively complemented so that each such selectively complemented data block includes less than the maximum number of logical transitions.In one embodiment, an input sequence of 9-bit data blocks is balanced to produce a DC-balanced sequence of characters. A shift register generator generates a pseudo-random binary sequence. Two bits of the pseudo-random binary sequence are logically combined to determine whether to invert another bit in the pseudo-random binary sequence, thereby cycling the pseudo-random binary sequence. A bit of the pseudo-random binary sequence is used as a criterion to selectively invert all the bits in the incoming 9-bit data block, thereby producing a 9-bit data block in an output stream that, over time, tends to be DC-balanced.

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