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1. 发明申请

US20070181969A1 Semiconductor memory device and method of fabricating the same 失效
标题翻译：半导体存储器件及其制造方法
公开(公告)号：US20070181969A1
公开(公告)日：2007-08-09
申请号：US11704300
申请日：2007-02-09
申请人： Kwang-duk Kim , Jong-hyun Ahn , Jeong-ho Shin
发明人： Kwang-duk Kim , Jong-hyun Ahn , Jeong-ho Shin
IPC分类号： H01L29/00
CPC分类号： H01L23/5256 , H01L27/112 , H01L27/11206 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor memory device having an improved fuse structure may include an interlayer insulating film on a semiconductor substrate, an opening in the interlayer insulating film, a vertical fuse that may conform to the opening, a fuse insulating film on the vertical fuse that may fill the opening, and metal wiring lines that may be electrically connected to the vertical fuse.
摘要翻译：具有改进的熔丝结构的半导体存储器件可以包括在半导体衬底上的层间绝缘膜，层间绝缘膜中的开口，可以符合开口的垂直熔丝，垂直保险丝上的熔丝绝缘膜可以填充开口和可以电连接到垂直保险丝的金属布线。

2. 发明授权

US07649240B2 Semiconductor memory device with vertical fuse 失效
标题翻译：具有垂直保险丝的半导体存储器件
公开(公告)号：US07649240B2
公开(公告)日：2010-01-19
申请号：US11704300
申请日：2007-02-09
申请人： Kwang-duk Kim , Jong-hyun Ahn , Jeong-ho Shin
发明人： Kwang-duk Kim , Jong-hyun Ahn , Jeong-ho Shin
IPC分类号： H01L29/00
CPC分类号： H01L23/5256 , H01L27/112 , H01L27/11206 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor memory device having an improved fuse structure may include an interlayer insulating film on a semiconductor substrate, an opening in the interlayer insulating film, a vertical fuse that may conform to the opening, a fuse insulating film on the vertical fuse that may fill the opening, and metal wiring lines that may be electrically connected to the vertical fuse.
摘要翻译：具有改进的熔丝结构的半导体存储器件可以包括在半导体衬底上的层间绝缘膜，层间绝缘膜中的开口，可以符合开口的垂直熔丝，垂直保险丝上的熔丝绝缘膜可以填充开口和可以电连接到垂直保险丝的金属布线。

3. 发明授权

US08419143B2 Structure for modifying height of shelf and refrigerator having the same 有权
标题翻译：具有相同的架子和冰箱高度的结构
公开(公告)号：US08419143B2
公开(公告)日：2013-04-16
申请号：US12596632
申请日：2008-04-18
申请人： Jeong-ho Shin , Byeong-gyu Kang , Jae-youl Lee , Ki-hoon Song
发明人： Jeong-ho Shin , Byeong-gyu Kang , Jae-youl Lee , Ki-hoon Song
IPC分类号： A47B96/04
CPC分类号： F25D25/02 , F25D25/04
摘要： The present invention relates to a shelf and a refrigerator, and more particularly, to a shelf height re-setting structure which enables convenient setting of a shelf without removing food from the shelf, and a refrigerator having the same. For this, the present invention provides a shelf height re-setting structure including a rail having height adjusting paths repeated in a vertical direction each with a slope and release and setting paths connected between adjacent height adjusting paths, and setting means secured to the shelf so as to be movable along the height adjusting paths and release and setting paths for selecting a height of the shelf, and a refrigerator with the same.
摘要翻译：搁板和冰箱技术领域本发明涉及搁板和冰箱，更具体地说，涉及一种架子高度重新设定结构，其能够方便地设置搁板而不将食物从架子上除去，以及具有该搁架结构的冰箱。为此，本发明提供了一种搁架高度重新设定结构，其包括轨道，该轨道具有在垂直方向上重复的高度调节路径，每个轨道具有连接在相邻的高度调节路径之间的斜坡和释放和设置路径，以及固定装置固定到搁架上可以沿着高度调节路径和用于选择搁板的高度的释放和设置路径以及具有该高度的冰箱。

4. 发明申请

US20060146675A1 Methods, systems and computer program products for recording data on and/or reproducing data from an optical disk 审中-公开
标题翻译：用于在光盘上记录和/或再现数据的数据的方法，系统和计算机程序产品
公开(公告)号：US20060146675A1
公开(公告)日：2006-07-06
申请号：US11313580
申请日：2005-12-21
申请人： Jeong-ho Shin
发明人： Jeong-ho Shin
IPC分类号： G11B5/09
CPC分类号： G11B20/1883 , G11B20/10 , G11B2220/20
摘要： Systems for recording data on and/or reproducing data from an optical disk are provided. The system includes a microcontroller unit (MCU) and a defect detector, electrically coupled to the MCU. The defect detector is configured to determine whether a data block is a defect block using a radio frequency (RF) signal generated when encoded write data is recorded in the data block and read Absolute Time In Pre-groove (ATIP) information which specifies the position of the defect block if it is determined that the data block is a defect block. The system further includes a storage unit electrically coupled to the defect detector. The storage unit is configured to store the ATIP information as defect position information and transmit the defect position information to the MCU. The MCU is further configured to control recordation of data, which is to be recorded in the defect block, in a spare area of an optical disk. The spare area is indicated in reassignment position information corresponding to the defect position information. Related methods and computer program products are also provided.
摘要翻译：提供了用于在光盘上记录数据和/或从光盘再现数据的系统。该系统包括一个电气耦合到MCU的微控制器单元（MCU）和缺陷检测器。缺陷检测器被配置为使用在编码的写入数据被记录在数据块中时产生的射频（RF）信号来确定数据块是否是缺陷块，并且读取指定位置的绝对时间预编码（ATIP）信息如果确定数据块是缺陷块，则为缺陷块。该系统还包括电连接到缺陷检测器的存储单元。存储单元被配置为将ATIP信息存储为缺陷位置信息，并将缺陷位置信息发送到MCU。 MCU还被配置为控制要记录在缺陷块中的数据在光盘的备用区中的记录。备用区域在对应于缺陷位置信息的再分配位置信息中指示。还提供了相关方法和计算机程序产品。

5. 发明授权

US06878598B2 Method of forming thick metal silicide layer on gate electrode 有权
标题翻译：在栅电极上形成厚金属硅化物层的方法
公开(公告)号：US06878598B2
公开(公告)日：2005-04-12
申请号：US10731761
申请日：2003-12-09
申请人： Jin-won Jun , Kong-soo Cheong , Jeong-ho Shin
发明人： Jin-won Jun , Kong-soo Cheong , Jeong-ho Shin
IPC分类号： H01L21/3205 , H01L21/336 , H01L21/4763
CPC分类号： H01L29/66507
摘要： Provided is a method of forming a thick metal silicide layer on a gate electrode. The method includes forming a gate electrode of a transistor on a semiconductor substrate, wherein a hard mask is formed on the gate electrode, forming a spacer on a sidewall of the gate electrode, forming a first silicide layer on a portion of the semiconductor substrate, adjacent to the spacer, forming an insulating layer on the first suicide layer to expose upper portions of the hard mask and the spacer, selectively etching the exposed upper portions of the hard mask and the spacer using the insulating layer as an etch mask until the top surface and the sidewall of the gate electrode are exposed, forming a metal layer on the exposed top surface and sidewall of the gate electrode, and forming a second silicide layer on the gate electrode by siliciding the metal layer.
摘要翻译：提供了在栅电极上形成厚金属硅化物层的方法。该方法包括在半导体衬底上形成晶体管的栅电极，其中在栅电极上形成硬掩模，在栅电极的侧壁上形成间隔物，在半导体衬底的一部分上形成第一硅化物层，在第一硅化物层上形成绝缘层以暴露硬掩模和间隔物的上部，使用绝缘层作为蚀刻掩模选择性地蚀刻硬掩模和间隔物的暴露的上部，直到顶部露出栅电极的侧壁，在露出的栅电极的顶表面和侧壁上形成金属层，并通过硅化金属层在栅电极上形成第二硅化物层。

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