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1. 发明授权

US08040201B2 Substrate having a structure for suppressing noise generated in a power plane and/or a ground plane, and an electronic system including the same 有权
标题翻译：具有用于抑制在电力平面和/或接地平面中产生的噪声的结构的基板，以及包括该基板的电子系统
公开(公告)号：US08040201B2
公开(公告)日：2011-10-18
申请号：US12354488
申请日：2009-01-15
申请人： Kwang-Soo Park , Byoung-Ha Oh , Yong-Ho Ko
发明人： Kwang-Soo Park , Byoung-Ha Oh , Yong-Ho Ko
IPC分类号： H04B3/30 , H01P3/08
CPC分类号： H05K1/0216 , H05K1/0234 , H05K1/0298 , H05K1/09 , H05K1/167 , H05K2201/0338 , H05K2201/0352 , H05K2201/09318 , H05K2201/09327
摘要： A substrate includes a power plane and a ground plane that are placed apart from and are substantially parallel to each other, and at least one signal line that is placed between the power plane and the ground plane. The ground plane includes a first conductive layer having a first conductivity. The power plane includes a second conductive layer having the first conductivity, and the power plane or the ground plane includes a third conductive layer having a second conductivity lower than the first conductivity. The third conductive layer faces the at least one signal line across a dielectric substance.
摘要翻译：基板包括放置在彼此之间并且基本上彼此平行的电源平面和接地平面以及放置在电源平面和接地平面之间的至少一条信号线。接地平面包括具有第一导电性的第一导电层。功率平面包括具有第一导电性的第二导电层，并且功率平面或接地平面包括具有比第一导电率低的第二导电性的第三导电层。第三导电层面对穿过电介质物质的至少一条信号线。

2. 发明申请

US20090184778A1 SUBSTRATE HAVING A STRUCTURE FOR SUPPRESSING NOISE GENERATED IN A POWER PLANE AND/OR A GROUND PLANE, AND AN ELECTRONIC SYSTEM INCLUDING THE SAME 有权
标题翻译：具有用于抑制在电力平面和/或地面平面中产生的噪声的结构的基板以及包括其的电子系统
公开(公告)号：US20090184778A1
公开(公告)日：2009-07-23
申请号：US12354488
申请日：2009-01-15
申请人： Kwang-Soo Park , Byoung-Ha Oh , Yong-Ho Ko
发明人： Kwang-Soo Park , Byoung-Ha Oh , Yong-Ho Ko
IPC分类号： H04B15/00
CPC分类号： H05K1/0216 , H05K1/0234 , H05K1/0298 , H05K1/09 , H05K1/167 , H05K2201/0338 , H05K2201/0352 , H05K2201/09318 , H05K2201/09327
摘要： A substrate includes a power plane and a ground plane that are placed apart from and are substantially parallel to each other, and at least one signal line that is placed between the power plane and the ground plane. The ground plane includes a first conductive layer having a first conductivity. The power plane includes a second conductive layer having the first conductivity, and the power plane or the ground plane includes a third conductive layer having a second conductivity lower than the first conductivity. The third conductive layer faces the at least one signal line across a dielectric substance.
摘要翻译：基板包括放置在彼此之间并且基本上彼此平行的电源平面和接地平面以及放置在电源平面和接地平面之间的至少一条信号线。接地平面包括具有第一导电性的第一导电层。功率平面包括具有第一导电性的第二导电层，并且功率平面或接地平面包括具有比第一导电率低的第二导电性的第三导电层。第三导电层面对穿过电介质物质的至少一条信号线。

3. 发明授权

US07821803B2 Memory module having star-type topology and method of fabricating the same 有权
标题翻译：具有星型拓扑的存储器模块及其制造方法
公开(公告)号：US07821803B2
公开(公告)日：2010-10-26
申请号：US12221728
申请日：2008-08-06
申请人： Do-Hyung Kim , Byoung-Ha Oh , Young-Jun Park , Yong-Ho Ko
发明人： Do-Hyung Kim , Byoung-Ha Oh , Young-Jun Park , Yong-Ho Ko
IPC分类号： G11C5/02
CPC分类号： G11C5/04 , G11C5/025 , Y10T29/49002
摘要： A memory module having a start-type topology and a method of fabricating the same are provided. The memory module includes a substrate. Memory devices are mounted on the substrate in at least two rows and at least two columns. A star-type topology is disposed to be electrically connected to the memory devices. One or more pairs of adjacent ones of the memory devices have a point-symmetric structure.
摘要翻译：提供具有起动型拓扑的存储器模块及其制造方法。存储器模块包括衬底。存储器件以至少两行和至少两列安装在衬底上。星型拓扑被布置成电连接到存储器件。一对或多对相邻的存储器件具有点对称结构。

4. 发明申请

US20090097297A1 Memory module having star-type topology and method of fabricating the same 有权
标题翻译：具有星型拓扑的存储器模块及其制造方法
公开(公告)号：US20090097297A1
公开(公告)日：2009-04-16
申请号：US12221728
申请日：2008-08-06
申请人： Do-Hyung Kim , Byoung-Ha Oh , Young-Jun Park , Yong-Ho Ko
发明人： Do-Hyung Kim , Byoung-Ha Oh , Young-Jun Park , Yong-Ho Ko
IPC分类号： G11C5/02 , H01S4/00 , G11C5/06
CPC分类号： G11C5/04 , G11C5/025 , Y10T29/49002
摘要： A memory module having a start-type topology and a method of fabricating the same are provided. The memory module includes a substrate. Memory devices are mounted on the substrate in at least two rows and at least two columns. A star-type topology is disposed to be electrically connected to the memory devices. One or more pairs of adjacent ones of the memory devices have a point-symmetric structure.
摘要翻译：提供具有起动型拓扑的存储器模块及其制造方法。存储器模块包括衬底。存储器件以至少两行和至少两列安装在衬底上。星型拓扑被布置成电连接到存储器件。一对或多对相邻的存储器件具有点对称结构。

5. 发明申请

US20080237314A1 Method of joining electronic package capable of prevention for brittle fracture 审中-公开
$Method of joining electronic package capable of prevention for brittle fracture$
标题翻译：连接能够预防脆性断裂的电子封装的方法
公开(公告)号：US20080237314A1
公开(公告)日：2008-10-02
申请号：US11907528
申请日：2007-10-12
申请人： Jin Yu , Young-Kun Jee , Yong-Ho Ko
发明人： Jin Yu , Young-Kun Jee , Yong-Ho Ko
IPC分类号： B23K31/02 , B23K1/00
CPC分类号： B23K1/0016 , B23K2101/34 , B23K2101/40 , B23K2103/18 , H01L2224/0554 , H01L2224/0557 , H01L2224/05571 , H01L2224/05573 , H01L2224/05647 , H01L2224/05655 , H01L2224/13 , H01L2224/16503 , H01L2224/8181 , H01L2924/00014 , H05K3/244 , H05K3/3463 , H01L2224/05599 , H01L2224/0555 , H01L2224/0556
摘要： Disclosed is a method of joining electronic package parts, comprising the steps of: reflowing lead-free solders containing alloy elements on top of each of the electronic package parts having a surface treated with copper or nickel; and mounting the surface treated electronic parts on the lead-free solders then reflowing the lead-free solders to generate intermetallic compound between the lead-free solders and the surface treated portion of each of the electronic parts.Alternatively, the method of joining the electronic package parts according to the present invention comprises the steps of: forming a plating layer made of alloy elements on top of each of the electronic parts having a surface treated with copper or nickel and reflowing lead-free solders; and mounting the surface treated electronic parts on the lead-free solders then reflowing the lead-free solders to allow the alloy elements contained in the plating layer to be diffused into the lead-free solders and generate intermetallic compound between the lead-free solders and the surface treated portion of each of the electronic parts.The present invention can prevent brittle fracture of the electronic package parts by deriving alteration of the intermetallic compounds generated from existing lead-free solders when the electronic package parts of electronic devices are solder joined together, thereby ensuring reliability of the electronic devices.
摘要翻译：公开了一种连接电子封装部件的方法，包括以下步骤：在具有用铜或镍处理的表面的每个电子封装部件的顶部上回流含有合金元素的无铅焊料; 并将表面处理的电子部件安装在无铅焊料上，然后回流无铅焊料，以在无铅焊料和每个电子部件的表面处理部分之间产生金属间化合物。或者，根据本发明的接合电子封装部件的方法包括以下步骤：在具有用铜或镍处理的表面的每个电子部件的顶部上形成由合金元件制成的镀层和回流无铅焊料 ; 并将表面处理的电子部件安装在无铅焊料上，然后回流无铅焊料，使包含在镀层中的合金元素扩散到无铅焊料中，并在无铅焊料与无铅焊料之间产生金属间化合物每个电子部件的表面处理部分。本发明可以通过在电子器件的电子封装部件焊接在一起时导致由现有的无铅焊料产生的金属间化合物的变化来防止电子封装部件的脆性断裂，从而确保电子器件的可靠性。

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