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1. 发明申请

US20050170891A1 Venus system 审中-公开
标题翻译：金星系统
公开(公告)号：US20050170891A1
公开(公告)日：2005-08-04
申请号：US10860304
申请日：2004-06-04
申请人： Kwang Shim , Yung Jung , Bum Lim , Jaeyong Chung , Il Park , Byoung Choi
发明人： Kwang Shim , Yung Jung , Bum Lim , Jaeyong Chung , Il Park , Byoung Choi
IPC分类号： G06F15/00 , A63F9/24 , A63F13/12 , G06F17/00 , G06F19/00
CPC分类号： A63F13/35 , A63F13/12 , A63F2300/535
摘要： A VENUS (Virtual Environment Network User Simulator) system, including: a VC (Virtual Client) agent for managing a plurality of VCs and providing a monitoring result; a server observer for transmitting a state of a server system by a request or periodically; a client observer for transmitting a state of a client system by a request or periodically; a testing game client for transmitting a state of an application program by using an API (Application Program Interface) provided from an observer library; a testing game server cluster for transmitting a state of an application program using the API provided from the observer library; and a CES (Central Engineering Station) for receiving an input from a user to setup a simulation environment, managing the VC agent, monitoring a network state and the state of the server system through the server observer, and monitoring the state of the client system through the client observer.
摘要翻译：一种VENUS（虚拟环境网络用户模拟器）系统，包括：用于管理多个VC并提供监视结果的VC（虚拟客户端）代理; 服务器观察器，用于通过请求或周期性地发送服务器系统的状态; 客户端观察器，用于通过请求或周期性地发送客户端系统的状态; 用于通过使用从观察者库提供的API（应用程序接口）来发送应用程序的状态的测试游戏客户端; 用于使用从观察者库提供的API发送应用程序的状态的测试游戏服务器集群; 以及CES（中央工程站），用于从用户接收用于设置仿真环境的输入，通过服务器观察器管理VC代理，监视网络状态和服务器系统的状态，以及监视客户端系统的状态通过客户观察员。

2. 发明申请

US20110138101A1 MAINTAINING DATA COHERENCE BY USING DATA DOMAINS 失效
标题翻译：通过使用数据域维护数据的一致性
公开(公告)号：US20110138101A1
公开(公告)日：2011-06-09
申请号：US12633428
申请日：2009-12-08
申请人： Kattamuri Ekanadham , Il Park , Pratap Pattnaik
发明人： Kattamuri Ekanadham , Il Park , Pratap Pattnaik
IPC分类号： G06F12/06
CPC分类号： G06F9/30007 , G06F12/0817 , G06F12/1027
摘要： A method, system and computer program product are disclosed for maintaining data coherence, for use in a multi-node processing system where each of the nodes includes one or more components. In one embodiment, the method comprises establishing a data domain, assigning a group of the components to the data domain, sending a coherence message from a first component of the processing system to a second component of the processing system, and determining if that second component is assigned to the data domain. In this embodiment, if that second component is assigned to the data domain, the coherence message is transferred to all of the components assigned to the data domain to maintain data coherency among those components. In an embodiment, if that second component is assigned to the data domain, the first component is assigned to the data domain.
摘要翻译：公开了用于维持数据一致性的方法，系统和计算机程序产品，用于多节点处理系统，其中每个节点包括一个或多个组件。在一个实施例中，该方法包括建立数据域，将一组组件分配给数据域，将相干消息从处理系统的第一组件发送到处理系统的第二组件，以及确定该第二组件被分配给数据域。在该实施例中，如果该第二组件被分配给数据域，则将相干消息传送到分配给数据域的所有组件，以维持这些组件之间的数据一致性。在一个实施例中，如果将该第二组件分配给数据域，则将第一组件分配给数据域。

3. 发明申请

US20090216956A1 SYSTEM, METHOD AND COMPUTER PROGRAM PRODUCT FOR ENHANCING TIMELINESS OF CACHE PREFETCHING 有权
标题翻译：系统，方法和计算机程序产品，用于增强缓存时间的推广
公开(公告)号：US20090216956A1
公开(公告)日：2009-08-27
申请号：US12036476
申请日：2008-02-25
申请人： Kattamuri Ekanadham , Jennifer A. Navarro , Il Park , Chung-Lung Kevin Shum
发明人： Kattamuri Ekanadham , Jennifer A. Navarro , Il Park , Chung-Lung Kevin Shum
IPC分类号： G06F12/08
CPC分类号： G06F12/0862 , G06F2212/6026
摘要： A system, method, and computer program product for enhancing timeliness of cache memory prefetching in a processing system are provided. The system includes a stride pattern detector to detect a stride pattern for a stride size in an amount of bytes as a difference between successive cache accesses. The system also includes a confidence counter. The system further includes eager prefetching control logic for performing a method when the stride size is less than a cache line size. The method includes adjusting the confidence counter in response to the stride pattern detector detecting the stride pattern, comparing the confidence counter to a confidence threshold, and requesting a cache prefetch in response to the confidence counter reaching the confidence threshold. The system may also include selection logic to select between the eager prefetching control logic and standard stride prefetching control logic.
摘要翻译：提供了一种用于增强处理系统中的高速缓存存储器预取的及时性的系统，方法和计算机程序产品。系统包括步幅图案检测器，用于检测作为连续高速缓存访问之间的差异的字节量的步幅大小的步幅图案。系统还包括置信柜台。该系统还包括用于当步幅大小小于高速缓存行大小时执行方法的迫切预取控制逻辑。该方法包括响应于步幅模式检测器检测步幅模式来调整置信计数器，将置信计数器与置信阈值进行比较，以及响应于达到置信阈值的置信度计数器请求高速缓存预取。系统还可以包括选择逻辑以在急切预取控制逻辑和标准步幅预取控制逻辑之间进行选择。

4. 发明申请

US20060049988A1 Antenna module and elctronic apparatus having the same 有权
标题翻译：天线模块和具有相同功能的电子装置
公开(公告)号：US20060049988A1
公开(公告)日：2006-03-09
申请号：US10983634
申请日：2004-11-09
申请人： Hyun Kim , Chul Kim , Jeong Seo , Il Park
发明人： Hyun Kim , Chul Kim , Jeong Seo , Il Park
IPC分类号： H01Q1/38
CPC分类号： H01Q1/243 , H01Q1/38 , H01Q9/0421 , H01Q21/0025
摘要： An antenna module, which minimizes a space, in an electronic apparatus set, occupied thereby without changing characteristics thereof, improves a degree of freedom of the installation structure thereof to increase the space utilization of the set, and achieves miniaturization and multi-functionality of electronic apparatuses, and an electronic apparatus having the antenna module. The antenna module includes a PCB (printed circuit board) made of nonconductive material having flexibility; an antenna element mounted at a designated position of the upper surface of the PCB; a ground line formed on the PCB so that the ground line is connected to a ground terminal of the antenna element, and provided with a joint portion formed at one end thereof; a feeder line formed on the PCB so that the feeder line is connected to a signal terminal of the antenna element, and provided with a joint portion formed at one end thereof; and a passive line, having a designated length, formed on the PCB in parallel with the feeder line. The joint portions of the ground line and the feeder line are bonded to designated positions of a set of the wireless electronic apparatus, and a portion of the antenna module having the antenna element mounted on the PCB is located outside the set.
摘要翻译：在不改变其特性的情况下使电子设备组中的空间最小化的天线模块提高了其安装结构的自由度，从而提高了组件的空间利用率，并实现了电子设备的小型化和多功能化装置和具有天线模块的电子装置。天线模块包括由具有柔性的非导电材料制成的PCB（印刷电路板）安装在PCB的上表面的指定位置的天线元件; 形成在PCB上的接地线，使得接地线连接到天线元件的接地端子，并且在其一端设置有接合部分; 形成在PCB上的馈电线，使得馈线与天线元件的信号端子连接，并且在其一端设置有接合部分; 以及具有指定长度的无源线，其与馈线相平行地形成在PCB上。接地线和馈电线的接合部分接合到一组无线电子设备的指定位置，并且具有安装在PCB上的天线元件的天线模块的一部分位于组外部。

5. 发明授权

US08667102B1 Module-based device interaction system 失效
标题翻译：基于模块的设备交互系统
公开(公告)号：US08667102B1
公开(公告)日：2014-03-04
申请号：US13585362
申请日：2012-08-14
申请人： Jason Thomas Winters , Il Park , Peter Hans Scharler
发明人： Jason Thomas Winters , Il Park , Peter Hans Scharler
IPC分类号： G06F15/16
CPC分类号： H04L67/141 , G06F9/54
摘要： A system that enables a person to monitor and/or control a device via a network, such as the Internet, via an interactive hardware module that interfaces with the device and communicates with a module server located locally or remotely from the placement of the module. The hardware module allows for the transmission and receipt of data between the device interfaced to the hardware module and the module server, thereby enabling the user manually or automatically to control or monitor the device via an access medium, such as an API.
摘要翻译：一种使人能够经由诸如因特网的网络经由与该设备接口并与本地或远离该模块的放置位置的模块服务器通信的交互式硬件模块来监视和/或控制设备的系统。硬件模块允许在连接到硬件模块的设备和模块服务器之间传输和接收数据，从而使用户能够手动或自动地通过诸如API的访问介质来控制或监视设备。

6. 发明授权

US08484422B2 Maintaining data coherence by using data domains 失效
标题翻译：通过使用数据域维护数据一致性
公开(公告)号：US08484422B2
公开(公告)日：2013-07-09
申请号：US12633428
申请日：2009-12-08
申请人： Kattamuri Ekanadham , Il Park , Pratap Pattnaik
发明人： Kattamuri Ekanadham , Il Park , Pratap Pattnaik
IPC分类号： G06F12/08
CPC分类号： G06F9/30007 , G06F12/0817 , G06F12/1027
摘要： A method, system and computer program product are disclosed for maintaining data coherence, for use in a multi-node processing system where each of the nodes includes one or more components. In one embodiment, the method comprises establishing a data domain, assigning a group of the components to the data domain, sending a coherence message from a first component of the processing system to a second component of the processing system, and determining if that second component is assigned to the data domain. In this embodiment, if that second component is assigned to the data domain, the coherence message is transferred to all of the components assigned to the data domain to maintain data coherency among those components. In an embodiment, if that second component is assigned to the data domain, the first component is assigned to the data domain.
摘要翻译：公开了用于维持数据一致性的方法，系统和计算机程序产品，用于多节点处理系统，其中每个节点包括一个或多个组件。在一个实施例中，该方法包括建立数据域，将一组组件分配给数据域，将相干消息从处理系统的第一组件发送到处理系统的第二组件，以及确定该第二组件被分配给数据域。在该实施例中，如果该第二组件被分配给数据域，则将相干消息传送到分配给数据域的所有组件，以维持这些组件之间的数据一致性。在一个实施例中，如果将该第二组件分配给数据域，则将第一组件分配给数据域。

7. 发明授权

US07900026B2 Target branch prediction using a plurality of tables 失效
标题翻译：使用多个表进行目标分支预测
公开(公告)号：US07900026B2
公开(公告)日：2011-03-01
申请号：US12246282
申请日：2008-10-06
申请人： Il Park , Mauricio J. Serrano , Jong-Deok Choi
发明人： Il Park , Mauricio J. Serrano , Jong-Deok Choi
IPC分类号： G06F9/32
CPC分类号： G06F9/3806 , G06F9/322 , G06F9/3848
摘要： A system for predicting multiple targets for a single branch includes: a branch target buffer that includes a previous next address for an instruction and that receives an indirect instruction address to provide a first branch target prediction; a first branch table for capturing local past target information of an indirect branch in an encoded form; a second branch table which is a correlation table for storing potential branch targets based on a local branch history and which provides a second branch target prediction when the first branch target prediction is not successful; an exclusion predictor for inhibiting updates of inefficient entries; and a multiplexer to select the predicted target as output.
摘要翻译：用于预测单个分支的多个目标的系统包括：分支目标缓冲器，其包括用于指令的先前的下一个地址并且接收间接指令地址以提供第一分支目标预测; 用于以编码形式捕获间接分支的当地过去目标信息的第一分支表; 第二分支表，其是基于本地分支历史存储潜在分支目标的相关表，并且当第一分支目标预测不成功时提供第二分支目标预测; 用于禁止更低效率条目的排除预测器; 以及选择预测目标作为输出的多路复用器。

8. 发明申请

US20070251064A1 Preventing Device of Sliding for Vehicle 失效
标题翻译：防止车辆滑动装置
公开(公告)号：US20070251064A1
公开(公告)日：2007-11-01
申请号：US11663019
申请日：2005-10-26
申请人： Il Park
发明人： Il Park
IPC分类号： B60C27/00
CPC分类号： B60C27/22 , Y10T24/45031 , Y10T152/10279
摘要： The present invention relates to a sliding prevention device for a vehicle, which includes a plurality of spikes, each of which is formed with a supporting device having a triangular shaped contacting portion including a wide surface facing toward the outer peripheral edge of the dual wheels and both right and left legs contacting between the dual wheels so that it can be supported between the tires of the dual wheels, a braking plate engaged with the supporting device in the outer peripheral edge of the dual wheels to produce the breaking power by contacting with the dual wheels, and an engaging portion formed at an inward apex between the tires of the dual wheels; an interval maintaining device adapted to engage with engaging portion of the spike by inserting a wire and maintain the intervals between the plurality of spikes; and a locking portion including a ring shaped locking hook formed at one end of the wire in the interval maintaining device, an engaging lever having a length adjusting device and an elastic body formed at the other end of the wire, and a thrust prevention device formed to project at a position of the spike to be engaged, whereby the locking hook is adjusted in length by the length adjusting device and the elastic body to thereby engage with the engaging lever with the thrust of the spike being prevented by the thrust preventing device at the state of installing the plurality of spikes to the dual wheels after the spikes have been engaged with each other by the interval maintaining device.
摘要翻译：本发明涉及一种车辆用滑动防止装置，其特征在于，具有多个突起，每个突起形成有支撑装置，所述支撑装置具有包括朝向所述双轮的外周缘的宽面的三角形接触部，右腿和右腿之间的双腿接触，使得其可以被支撑在双轮的轮胎之间，制动板与双轮的外周边缘中的支撑装置接合，以通过与双轮的接触而产生断裂力双轮，以及形成在双轮轮胎之间的向内顶点处的接合部分; 间隔保持装置，其适于通过插入线并保持所述多个尖峰之间的间隔而与所述钉的接合部分接合; 以及锁定部，其包括形成在所述间隔保持装置中的所述线的一端的环形锁定钩，具有长度调节装置的接合杆和形成在所述线的另一端的弹性体，以及形成的推力防止装置突出在待钉入的钉的位置处，由此通过长度调节装置和弹性体来调节锁钩的长度，从而与接合杆接合，由防止推力装置防止钉的推力在通过间隔维持装置彼此接合尖峰之后将多个尖峰安装到双轮的状态。

9. 发明申请

US20050224880A1 Multi-gate MOS transistor and method of manufacturing the same 有权
标题翻译：多栅极MOS晶体管及其制造方法
公开(公告)号：US20050224880A1
公开(公告)日：2005-10-13
申请号：US11012695
申请日：2004-12-16
申请人： Dae Lee , Tae Roh , Sung Kwon , Il Park , Yil Yang , Byoung Yu , Jong Kim
发明人： Dae Lee , Tae Roh , Sung Kwon , Il Park , Yil Yang , Byoung Yu , Jong Kim
IPC分类号： H01L21/336 , H01L29/423 , H01L29/78 , H01L29/786
CPC分类号： H01L29/785 , H01L29/42384 , H01L29/42392 , H01L29/66795 , H01L29/78645
摘要： Provided are a multi-gate MOS transistor and a method of manufacturing the same. Two silicon fins are vertically stacked on a silicon on insulator (SOI) substrate, and four side surfaces of an upper silicon fin and three side surfaces of a lower silicon fin are used as a channel. Therefore, a channel width is increased, so that current driving capability of a device is improved, and high performance nano-level semiconductor IC and highly integrated memory IC can be manufactured through the optimization and stability of a process.
摘要翻译：提供一种多栅极MOS晶体管及其制造方法。垂直堆叠在硅绝缘体（SOI）基板上的两个硅散热片，上硅片的四个侧表面和下硅片的三个侧表面用作通道。因此，通道宽度增加，从而提高了器件的电流驱动能力，并且可以通过工艺的优化和稳定性来制造高性能纳米级半导体IC和高度集成的存储器IC。

10. 发明申请

US20150081989A1 SEMICONDUCTOR DEVICES INCLUDING APPLICATION PROCESSOR CONNECTED TO HIGH-BANDWIDTH MEMORY AND LOW-BANDWIDTH MEMORY, AND CHANNEL INTERLEAVING METHOD THEREOF 有权
标题翻译：包括连接到高带宽存储器和低带宽存储器的应用处理器的半导体器件及其通道交换方法
公开(公告)号：US20150081989A1
公开(公告)日：2015-03-19
申请号：US14307994
申请日：2014-06-18
申请人： Sung Hyun Lee , Jun Hee Yoo , Dongsoo Kang , Il Park , Kiyeon Lee , Euicheol Lim
发明人： Sung Hyun Lee , Jun Hee Yoo , Dongsoo Kang , Il Park , Kiyeon Lee , Euicheol Lim
IPC分类号： G06F12/06
CPC分类号： G06F12/0607 , Y02D10/13
摘要： A memory system includes a high-bandwidth memory device, the high-bandwidth memory device having a relatively high operation bandwidth, the high-bandwidth memory device having a plurality of access channels. A low-bandwidth memory device has a relatively low operation bandwidth relative to the high-bandwidth memory device, the low-bandwidth memory device having one or more access channels. An interleaving unit performs a memory interleave operation among the plurality of access channels of the high-bandwidth memory device and an access channel of the one or more access channels of the low-bandwidth memory device.
摘要翻译：存储器系统包括高带宽存储器件，具有相对高的操作带宽的高带宽存储器件，高带宽存储器件具有多个存取通道。低带宽存储器件相对于高带宽存储器件具有相对低的操作带宽，低带宽存储器件具有一个或多个存取通道。交织单元在高带宽存储装置的多个接入信道和低带宽存储装置的一个以上的接入信道的接入信道之间进行存储器交织操作。

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