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1. 发明申请

US20090121786A1 SEMICONDUCTOR INTEGRATED CIRCUIT 有权
标题翻译：半导体集成电路
公开(公告)号：US20090121786A1
公开(公告)日：2009-05-14
申请号：US12166085
申请日：2008-07-01
申请人： Kwan Weon Kim , Jun Ho Lee , Kun Woo Park , Chang Kyu Choi , Yong Ju Kim , Sung Woo Han , Jun Woo Lee
发明人： Kwan Weon Kim , Jun Ho Lee , Kun Woo Park , Chang Kyu Choi , Yong Ju Kim , Sung Woo Han , Jun Woo Lee
IPC分类号： H03K5/00
CPC分类号： H03K19/00369
摘要： A semiconductor integrated circuit can include a first voltage pad, a second voltage pad, and a voltage stabilizing unit that is connected between the first voltage pad and the second voltage pad. The first voltage pad can be connected to a first internal circuit, and the second voltage pad can be connected to a second internal circuit.
摘要翻译：半导体集成电路可以包括连接在第一电压焊盘和第二电压焊盘之间的第一电压焊盘，第二电压焊盘和稳压单元。第一电压焊盘可以连接到第一内部电路，并且第二电压焊盘可以连接到第二内部电路。

2. 发明授权

US07911251B2 Clock signal generating circuit and semiconductor memory apparatus including the same 失效
标题翻译：时钟信号发生电路和包括该电路的半导体存储装置
公开(公告)号：US07911251B2
公开(公告)日：2011-03-22
申请号：US12494814
申请日：2009-06-30
申请人： Hyeng Ouk Lee , Kwan Weon Kim
发明人： Hyeng Ouk Lee , Kwan Weon Kim
IPC分类号： G06F1/04
CPC分类号： G01R23/15 , G06F1/06 , G06F1/3237 , G11C7/222 , Y02D10/128
摘要： A clock signal generating circuit includes a main clock buffering unit and a sub clock buffering unit. The main clock buffering unit is capable of generating both a differential clock signal pair and a single clock signal. The main clock buffering unit selectively outputs either the differential clock signal pair or the single clock signal depending upon the frequency of an external clock signal. The sub clock buffering unit receives the output of the main clock buffering unit and generates first and second clock signals. The operation of the sub clock buffering unit depends upon whether the differential clock signal pair or the single clock signal is output by the main clock buffering unit.
摘要翻译：时钟信号发生电路包括主时钟缓冲单元和子时钟缓冲单元。主时钟缓冲单元能够产生差分时钟信号对和单个时钟信号。主时钟缓冲单元根据外部时钟信号的频率有选择地输出差分时钟信号对或单个时钟信号。子时钟缓冲单元接收主时钟缓冲单元的输出并产生第一和第二时钟信号。子时钟缓冲单元的操作取决于差分时钟信号对或单个时钟信号是否由主时钟缓冲单元输出。

3. 发明授权

US08064283B2 Semiconductor memory apparatus and a method for reading data stored therein 有权
标题翻译：半导体存储装置及其中存储的数据的读取方法
公开(公告)号：US08064283B2
公开(公告)日：2011-11-22
申请号：US12470836
申请日：2009-05-22
申请人： Seung Wook Kwak , Kwan Weon Kim
发明人： Seung Wook Kwak , Kwan Weon Kim
IPC分类号： G11C8/00
CPC分类号： G11C7/1006 , G11C7/02 , G11C7/1048
摘要： A semiconductor memory apparatus includes a data bus inversion (DBI) section configured to receive a plurality of input data and decide whether to invert or output, without an inversion, the plurality of input data depending upon logic levels of the plurality of data, and further configured to generate a plurality of inversion data based on the decision; and a data output section configured to receive the plurality of inversion data, invert or output, without an inversion the plurality of inversion data in response to a mode signal, and generate a plurality of output data.
摘要翻译：一种半导体存储装置，包括：数据总线反相（DBI）部分，被配置为接收多个输入数据，并根据多个数据的逻辑电平决定是否反转输出多个输入数据，被配置为基于所述决定生成多个反转数据; 以及数据输出部，被配置为响应于模式信号而不反转或反转所述多个反转数据来反转或输出所述多个反转数据，并且生成多个输出数据。

4. 发明授权

US6137739A Multilevel sensing circuit and method thereof 有权
标题翻译：多电平检测电路及其方法
公开(公告)号：US6137739A
公开(公告)日：2000-10-24
申请号：US342176
申请日：1999-06-29
申请人： Kwan Weon Kim
发明人： Kwan Weon Kim
IPC分类号： G11C7/06 , G11C11/4091 , G11C11/56 , G11C7/00
CPC分类号： G11C7/062 , G11C11/4091 , G11C11/565 , G11C7/06
摘要： A multilevel sensing circuit and sensing method therefor. The multilevel sensing circuit has first and second sense amplifiers connected to each bit line to which left and right memory cells of a DRAM are connected, a feedback element connected to each bit line, and an isolating transistor including an NMOS transistor connected between the comparator and a sensing input node of the second sense amplifier. The isolating transistor is turned on after a second sensing operation is sufficiently carried out and turned off before a restore operation is carried out.
摘要翻译：一种多电平感测电路及其感测方法。多电平感测电路具有连接到每个位线的第一和第二读出放大器，DRAM的左和右存储单元连接到该位线，连接到每个位线的反馈元件以及连接在比较器和第二读出放大器的感测输入节点。在执行恢复操作之后，在充分执行第二感测操作并关闭之后，隔离晶体管导通。

5. 发明申请

US20090058458A1 DIGITAL-TO-ANALOG CONVERTING CIRCUIT AND APPARATUS FOR ON-DIE TERMINATION USING THE SAME 有权
标题翻译：数字到模拟转换电路和使用其进行在线终止的装置
公开(公告)号：US20090058458A1
公开(公告)日：2009-03-05
申请号：US12026465
申请日：2008-02-05
申请人： Kwan Weon Kim
发明人： Kwan Weon Kim
IPC分类号： H03K19/003 , H03M1/66
CPC分类号： G11C7/1051 , G11C7/1057 , H03M1/1057 , H03M1/808 , H04L25/0278
摘要： A digital-to-analogue converting circuit includes a driver leg having a plurality of resistance elements between a power supply voltage terminal and a ground voltage terminal, wherein at least one of the plurality of resistance elements is a variable resistor, and a code level changing unit for outputting a level-changed code to a control terminal of the variable resistor based on an activation of a digital code, wherein the level-changed code is produced by converting a level of the digital code.
摘要翻译：数模转换电路包括在电源电压端和地电压端之间具有多个电阻元件的驱动器支脚，其中多个电阻元件中的至少一个是可变电阻器，并且代码电平变化单元，用于基于数字代码的激活将电平变化的代码输出到可变电阻器的控制端子，其中通过转换数字代码的电平来产生电平变化的代码。

6. 发明授权

US07443738B2 Data transfer apparatus in semiconductor memory device and method of controlling the same 有权
标题翻译：半导体存储器件中的数据传送装置及其控制方法
公开(公告)号：US07443738B2
公开(公告)日：2008-10-28
申请号：US10878831
申请日：2004-06-28
申请人： Seung Wook Kwack , Kwan Weon Kim
发明人： Seung Wook Kwack , Kwan Weon Kim
IPC分类号： G11C7/10
CPC分类号： G11C7/1066 , G11C7/1051
摘要： Provided is directed to a circuit for controlling data and a data strobe driver in a semiconductor memory device, including: a first delay unit for outputting a data signal with a variable delay; a DQ driver for outputting a data signal according to the data signal passed through the first delay unit and a driver select signal; a second delay unit for outputting a data strobe signal with a variable delay; and a DQS driver for outputting the data strobe signal passed through the second delay unit by being driven according to the driver select signal.
摘要翻译：本发明涉及一种用于控制数据的电路和半导体存储器件中的数据选通驱动器，包括：用于输出具有可变延迟的数据信号的第一延迟单元; 用于根据通过第一延迟单元的数据信号输出数据信号的DQ驱动器和驱动器选择信号; 第二延迟单元，用于输出具有可变延迟的数据选通信号; 以及DQS驱动器，用于根据驱动器选择信号来驱动通过第二延迟单元的数据选通信号。

7. 发明申请

US20070285294A1 Apparatus and method of generating reference voltage of semiconductor integrated circuit 有权
标题翻译：生成半导体集成电路参考电压的装置和方法
公开(公告)号：US20070285294A1
公开(公告)日：2007-12-13
申请号：US11647482
申请日：2006-12-29
申请人： Kwan Weon Kim
发明人： Kwan Weon Kim
IPC分类号： H03M1/78
CPC分类号： G11C5/143
摘要： An apparatus for generating a reference voltage of a semiconductor integrated circuit includes a resistance control unit that adjusts at least one an adjustment code such that at least one set of resistors, which have resistances determined according to the at least one adjustment code have predetermined resistances, a voltage level control unit that generates a selection code for selecting the level of a final reference voltage under external control and outputs the generated selection code, and a reference voltage generating unit that converts a power supply voltage according to the adjustment code and the selection code and outputs the final reference voltage.
摘要翻译：一种用于产生半导体集成电路的参考电压的装置包括：电阻控制单元，其调整至少一个调整代码，使得至少一组具有根据至少一个调整代码确定的电阻的电阻器具有预定电阻，电压电平控制单元，其生成用于选择外部控制下的最终参考电压的电平的选择码，并输出所生成的选择码;以及参考电压生成单元，其根据调整码和选择码转换电源电压并输出最终参考电压。

8. 发明授权

US07227403B2 Internal voltage generator for semiconductor device 失效
标题翻译：半导体器件内部电压发生器
公开(公告)号：US07227403B2
公开(公告)日：2007-06-05
申请号：US11108493
申请日：2005-04-18
申请人： Kwan Weon Kim
发明人： Kwan Weon Kim
IPC分类号： G05F1/00
CPC分类号： H02M3/07 , G11C5/145
摘要： Disclosed is an internal voltage generator, which includes a detecting means for detecting a level of an internal voltage, an oscillator for generating a driving pulse signal in response to an output signal of the detecting means, a first driving unit for outputting a first pulse signal after receiving the driving pulse signal, a second driving unit for outputting a second pulse signal after receiving the driving pulse signal, and a pumping unit for changing a potential level of the internal voltage after selectively receiving one of the first pulse signal and the second pulse signal.
摘要翻译：公开了一种内部电压发生器，其包括用于检测内部电压电平的检测装置，响应于检测装置的输出信号产生驱动脉冲信号的振荡器，第一驱动单元，用于输出第一脉冲信号在接收到驱动脉冲信号之后的第二驱动单元，用于在接收到驱动脉冲信号之后输出第二脉冲信号;以及泵送单元，用于在选择性地接收第一脉冲信号和第二脉冲之一之后改变内部电压的电位电平信号。

9. 发明授权

US06859412B1 Circuit for controlling driver strengths of data and data strobe in semiconductor device 有权
标题翻译：用于控制半导体器件中数据和数据选通的驱动强度的电路
公开(公告)号：US06859412B1
公开(公告)日：2005-02-22
申请号：US10744993
申请日：2003-12-23
申请人： Seung Wook Kwack , Kwan Weon Kim
发明人： Seung Wook Kwack , Kwan Weon Kim
IPC分类号： G11C11/407 , G11C7/10 , G11C8/06 , G11C11/401
CPC分类号： G11C7/1057 , G11C7/1045 , G11C7/1051
摘要： A circuit for controlling driver strengths of a data and a data strobe in a semiconductor device comprising: a control signal generating unit which generates a first control signal in response to a first address code, generates a second control signal in response to a second address code, and generates a third control signal in response to a third address code; a data driver strength control unit which is selected in response to the first control signal, controls a driver strength of an input data in response to the second control signal, and finely adjusts the driver strength of the input data in response to the third control signal; and a data strobe driver strength control unit which is selected in response to the first control signal, controls a driver strength of an input data strobe in response to the second control signal, and finely adjusts the driver strength of the input data strobe in response to the third control signal.
摘要翻译：一种用于控制半导体器件中的数据和数据选通的驱动器强度的电路，包括：控制信号产生单元，其响应于第一地址码产生第一控制信号，响应于第二地址码产生第二控制信号并且响应于第三地址码产生第三控制信号; 响应于第一控制信号选择的数据驱动器强度控制单元响应于第二控制信号控制输入数据的驱动器强度，并且响应于第三控制信号精细地调整输入数据的驱动器强度 ; 以及响应于第一控制信号选择的数据选通驱动器强度控制单元，响应于第二控制信号控制输入数据选通的驱动器强度，并且响应于第二控制信号精确地调整输入数据选通的驱动器强度第三控制信号。

10. 发明授权

US08237464B2 Integrated circuit and method for controlling data output impedance 有权
标题翻译：用于控制数据输出阻抗的集成电路和方法
公开(公告)号：US08237464B2
公开(公告)日：2012-08-07
申请号：US13033845
申请日：2011-02-24
申请人： Ja Beom Koo , Kwan Weon Kim
发明人： Ja Beom Koo , Kwan Weon Kim
IPC分类号： H03K17/16 , H03K19/003
CPC分类号： G11C7/1051 , G11C7/1057 , G11C7/1072 , G11C8/08 , G11C29/02 , G11C29/022 , G11C29/028 , G11C29/50008 , G11C2207/2254
摘要： An integrated circuit for controlling data output impedance includes an address decoder, a selection signal decoder, and a transfer control unit. The address decoder is configured to decode an address signal and generate a selection mode signal and a first adjustment mode signal. The selection signal decoder is configured to decode a selection signal and generate an enable signal and a disable signal. The transfer control unit is configured to transfer a pull-up signal and a pull-down signal as a selection pull-up signal and a selection pull-down signal.
摘要翻译：用于控制数据输出阻抗的集成电路包括地址解码器，选择信号解码器和传送控制单元。地址解码器被配置为解码地址信号并产生选择模式信号和第一调整模式信号。选择信号解码器被配置为对选择信号进行解码并产生使能信号和禁用信号。传送控制单元被配置为传送上拉信号和下拉信号作为选择上拉信号和选择下拉信号。

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