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    • 4. 发明授权
    • LDPC decoding apparatus and method with low computational complexity algorithm
    • 具有低计算复杂度算法的LDPC解码装置和方法
    • US07539920B2
    • 2009-05-26
    • US11265451
    • 2005-11-02
    • Eun-A ChoiNae-Soo KimDeock-Gil OhJi-Won Jung
    • Eun-A ChoiNae-Soo KimDeock-Gil OhJi-Won Jung
    • H03M13/00
    • H03M13/11
    • Provided are an LDPC decoding apparatus and method using a sequential decoding algorithm having a partial group, capable of reducing the number of an iterative decoding by more than half without degrading the performance and increasing an amount of computation. The LDPC decoding method includes the steps of: receiving a prior probability information (channel values) based on information on channel values associated with distance between symbol signals in constellation related to the received noise and LDPC encoded data, and initializing bit nodes; dividing check nodes into partial groups before updating check node information based on the prior probability information, and performing a decoding by applying a sequential decoding algorithm; determining whether a parity check equations are satisfied; and outputting decoded messages obtained when satisfying the parity check equation or after terminating an iterative processor by a termination algorithm.
    • 提供了一种使用具有部分组的顺序解码算法的LDPC解码装置和方法,其能够将迭代解码的数量减少一半以上,而不降低性能并增加计算量。 LDPC解码方法包括以下步骤:基于与接收到的噪声相关的星座中的符号信号与LDPC编码数据之间的距离相关的信道值的信息,以及初始化比特节点,接收先验概率信息(信道值) 在根据先验概率信息更新校验节点信息之前,将校验节点划分为部分组,并通过应用顺序解码算法执行解码; 确定是否满足奇偶校验方程; 并输出在满足奇偶校验方程时获得的解码消息,或者通过终止算法终止迭代处理器。
    • 5. 发明申请
    • LDPC decoding apparatus and method using type-classified index
    • LDPC解码装置和方法使用类型分类指标
    • US20070150789A1
    • 2007-06-28
    • US11607592
    • 2006-11-30
    • Eun-A ChoiDae-Ig ChangDeock-Gil Oh
    • Eun-A ChoiDae-Ig ChangDeock-Gil Oh
    • H03M13/00
    • H03M13/1165H03M13/1111
    • Provided is a low-density parity-check (LDPC) decoding apparatus and method using a type-classified index. The apparatus includes: a memory allocating unit for multiplying reception data by an estimated channel value and storing a multiplied value in a memory including a plurality of memory block; an index storing unit for storing a Read Only Memory (ROM) index, an address index and a permutation index for the stored data; a check node updating unit for bring the stored data in parallel based on the ROM index, the address index, and the permutation index and updating a check node; and a bit node updating unit for updating a bit node based on the data stored in the memory and check node information updated in the check node updating unit.
    • 提供了一种使用类型分类索引的低密度奇偶校验(LDPC)解码装置和方法。 该装置包括:存储器分配单元,用于将接收数据乘以估计的信道值,并将乘法值存储在包括多个存储块的存储器中; 索引存储单元,用于存储所存储的数据的只读存储器(ROM)索引,地址索引和置换索引; 检查节点更新单元,用于基于所述ROM索引,所述地址索引和所述置换索引并行存储所述数据,并更新校验节点; 以及位节点更新单元,用于基于存储在存储器中的数据更新位节点,并且校验在校验节点更新单元中更新的节点信息。
    • 8. 发明授权
    • Structure and method for depuncturing punctured codes for radix-4 branch metric calculation in high-speed viterbi decoder
    • 用于在高速维特比解码器中进行基数4分支度量计算的去穿孔穿孔码的结构和方法
    • US06732326B2
    • 2004-05-04
    • US09846477
    • 2001-04-30
    • Eun-A ChoiJin-Ho KimNae-Soo KimDeock-Gil Oh
    • Eun-A ChoiJin-Ho KimNae-Soo KimDeock-Gil Oh
    • H03M1341
    • H03M13/6362H03M13/395H03M13/3961H03M13/41H03M13/4107
    • A structure and a method for depuncturing an input bit stream being input to a Viterbi decoder when the Viterbi decoder is designed by using a Radix-4 branch metric calculator in a method for designing the Viterbi decoder that decodes a punctured code at a high-speed, are disclosed. A depuncture structure for Radix-4 branch metric calculation in a high-speed Viterbi decoder includes four FIFOs, four multiplexers, and one Radix-4 branch metric calculator. Two input bit streams of I and Q are connected to two upper FIFOs and two lower FIFOs. An output terminal of FIFO is connected to upper and lower multiplexers of the next stage. One output terminal of each multiplexer is connected to Radix-4 branch metric calculator. As a result, Radix-4 branch metric calculation can be achieved by using the same clock as a clock speed of the input I and Q bit streams. This structure and this method can be applied to a depuncturing process for Radix-4 branch metric calculation of all punctured codes derived from ½ code.
    • 在维特比解码器被设计成通过在设计维特比解码器的方法中设计的维特比解码器的结构和方法被输入到维特比解码器,该维特比解码器以高速解码穿孔码 ,被披露。 在高速维特比解码器中用于基数4分支度量计算的解穿孔结构包括四个FIFO,四个多路复用器和一个基数-4分支度量计算器。 I和Q的两个输入比特流连接到两个较高的FIFO和两个较低的FIFO。 FIFO的输出端子连接到下一级的上下复用器。 每个多路复用器的一个输出端连接到基数-4分支度量计算器。 因此,可以通过使用与输入I和Q位流的时钟速度相同的时钟来实现基数-4分支度量计算。 该结构和该方法可以应用于从½码导出的所有穿孔码的基数-4分支度量计算的解穿孔过程。
    • 9. 发明授权
    • LDPC decoding apparatus and method using type-classified index
    • LDPC解码装置和方法使用类型分类指标
    • US08122315B2
    • 2012-02-21
    • US11607592
    • 2006-11-30
    • Eun-A ChoiDae-Ig ChangDeock-Gil Oh
    • Eun-A ChoiDae-Ig ChangDeock-Gil Oh
    • H03M13/00
    • H03M13/1165H03M13/1111
    • Provided is a low-density parity-check (LDPC) decoding apparatus and method using a type-classified index. The apparatus includes: a memory allocating unit for multiplying reception data by an estimated channel value and storing a multiplied value in a memory including a plurality of memory block; an index storing unit for storing a Read Only Memory (ROM) index, an address index and a permutation index for the stored data; a check node updating unit for bring the stored data in parallel based on the ROM index, the address index, and the permutation index and updating a check node; and a bit node updating unit for updating a bit node based on the data stored in the memory and check node information updated in the check node updating unit.
    • 提供了一种使用类型分类索引的低密度奇偶校验(LDPC)解码装置和方法。 该装置包括:存储器分配单元,用于将接收数据乘以估计的信道值,并将乘法值存储在包括多个存储块的存储器中; 索引存储单元,用于存储所存储的数据的只读存储器(ROM)索引,地址索引和置换索引; 检查节点更新单元,用于基于所述ROM索引,所述地址索引和所述置换索引并行存储所述数据,并更新校验节点; 以及位节点更新单元,用于基于存储在存储器中的数据更新位节点,并且校验在校验节点更新单元中更新的节点信息。
    • 10. 发明授权
    • Apparatus and method for decoding turbo TCM using coset mapping
    • 使用陪集映射对turbo TCM进行解码的装置和方法
    • US07613103B2
    • 2009-11-03
    • US10934000
    • 2004-09-03
    • Eun-A ChoiNae-Soo KimJi-Won Jung
    • Eun-A ChoiNae-Soo KimJi-Won Jung
    • H04J11/00
    • H04L1/005H04L1/006H04L1/0066H04L1/0071H04L27/186
    • A turbo TCM decoder for performing a soft decision without performing a sector phase quantization is disclosed. The turbo TCM decoder includes: a symbol transformer for converting a received signal to signal bits of QPSK mode by using an I-axis coordinate and a Q-axis coordinate on a constellation of the received signal; a phase sector quantizer for performing a phase sector quantization or the received signal by using the I-axis coordinate and the Q-axis coordinate; a first decoder for determining coded data by decoding the converted signal bits; a delay for delaying the quantized signal; and a second decoder for determining un-coded data by using the delayed quantized signal and the determined coded data.
    • 公开了一种用于在不执行扇区相位量化的情况下执行软判决的turbo TCM解码器。 涡轮TCM解码器包括:符号变换器,用于通过使用接收信号的星座上的I轴坐标和Q轴坐标将接收信号转换为QPSK模式的信号位; 相位扇区量化器,用于通过使用I轴坐标和Q轴坐标来执行相位扇区量化或接收信号; 第一解码器,用于通过解码转换的信号位来确定编码数据; 用于延迟量化信号的延迟; 以及第二解码器,用于通过使用延迟量化信号和所确定的编码数据来确定未编码数据。