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1. 发明授权

US5679589A FET with gate spacer 失效
标题翻译： FET带栅极间隔
公开(公告)号：US5679589A
公开(公告)日：1997-10-21
申请号：US866942
申请日：1992-04-03
申请人： Kuo-Hua Lee , Chih-Yuan Lu , Janmye Sung
发明人： Kuo-Hua Lee , Chih-Yuan Lu , Janmye Sung
IPC分类号： H01L21/265 , H01L21/336 , H01L29/78 , H01L21/28
CPC分类号： H01L29/66575 , H01L29/6656 , H01L29/6659 , H01L29/78
摘要： A semiconductor integrated circuit structure and method of fabrication is disclosed. The structure includes a FET gate with adjacent double or triple layered gate spacers. The spacers permit precise tailoring of lightly doped drain junction profiles having deep and shallow junction portions. In addition, a self-aligned silicide may be formed solely over the deep junction portion thus producing a reliable low contact resistance connection to source and drain.
摘要翻译：公开了一种半导体集成电路结构及其制造方法。该结构包括具有相邻的双层或三层栅极间隔物的FET栅极。间隔物允许精细地定制具有深浅接合部分的轻掺杂漏极结型材。此外，自对准硅化物可以仅形成在深结部分上方，从而产生与源极和漏极的可靠的低接触电阻连接。

2. 发明授权

US5879997A Method for forming self aligned polysilicon contact 失效
标题翻译：用于形成自对准多晶硅接触的方法
公开(公告)号：US5879997A
公开(公告)日：1999-03-09
申请号：US707365
申请日：1991-05-30
申请人： Kuo-Hua Lee , Janmye Sung
发明人： Kuo-Hua Lee , Janmye Sung
IPC分类号： H01L29/78 , H01L21/285 , H01L21/336 , H01L21/60
CPC分类号： H01L21/76897 , H01L21/28525 , H01L29/41783 , H01L29/66575
摘要： A gate contact to a field effect transistor is opened over the source/drain region by forming polysilicon plugs between the gate structure, which has a nitride top layer, and the field oxide regions. The contacts are formed by oxidizing and etching the gate structure and the polysilicon plugs. An oxide layer may be deposited prior to the etching. The latter step opens a gate contact but does not expose the silicon in the plug because the different oxidation rates of the polysilicon plug and the material on top of the gate structure create oxide layers having different thicknesses. The nitride is now removed and contacts formed to the gate structure.
摘要翻译：通过在具有氮化物顶层的栅极结构和场氧化物区域之间形成多晶硅插塞，在源极/漏极区域上开启与场效应晶体管的栅极接触。通过氧化和蚀刻栅极结构和多晶硅插塞来形成触点。在蚀刻之前可以沉积氧化物层。后一步骤打开栅极接触，但是不会将硅暴露在插塞中，因为多晶硅插塞的不同氧化速率和栅极结构顶部的材料产生具有不同厚度的氧化物层。现在去除氮化物，并将触点形成到栅极结构。

3. 发明授权

US5488248A Memory integrated circuit 失效
标题翻译：内存集成电路
公开(公告)号：US5488248A
公开(公告)日：1996-01-30
申请号：US446091
申请日：1995-05-19
申请人： Kuo-Hua Lee , Janmye Sung
发明人： Kuo-Hua Lee , Janmye Sung
IPC分类号： H01L21/8244 , H01L27/11 , H01L27/085
CPC分类号： H01L27/1108 , Y10S257/904
摘要： An integrated circuit, illustratively an SRAM, having a low resistance path between an access transistor and a pull down transistor is disclosed. Connection for the cell load to the node between the access transistor and pull down transistor is made outside the defined current path.
摘要翻译：公开了一种在存取晶体管和下拉晶体管之间具有低电阻路径的集成电路，例如SRAM。在存在晶体管和下拉晶体管之间的节点的电池负载的连接在限定的电流路径之外。

4. 发明授权

US5153145A FET with gate spacer 失效
标题翻译：带栅极间隔的FET
公开(公告)号：US5153145A
公开(公告)日：1992-10-06
申请号：US422834
申请日：1989-10-17
申请人： Kuo-Hua Lee , Chih-Yuan Lu , Janmye Sung
发明人： Kuo-Hua Lee , Chih-Yuan Lu , Janmye Sung
IPC分类号： H01L21/265 , H01L21/336 , H01L29/78
CPC分类号： H01L29/66575 , H01L29/6656 , H01L29/6659 , H01L29/78
摘要： A semiconductor integrated circuit structure and method of fabrication is disclosed. The structure includes a FET gate with adajcent double or triple-layered gate spacers. The spacers permit precise tailoring of lightly doped drain junction profiles having deep and shallow junction portions. In addition, a self-aligned silicide may be formed solely over the deep junction portion thus producing a reliable low contact resistance connection to source and drain.

5. 发明授权

US5353245A Memory integrated circuit with balanced resistance 失效
标题翻译：具有平衡电阻的存储器集成电路
公开(公告)号：US5353245A
公开(公告)日：1994-10-04
申请号：US111033
申请日：1993-08-24
申请人： Kuo-Hua Lee , Janmye Sung
发明人： Kuo-Hua Lee , Janmye Sung
IPC分类号： H01L21/8244 , H01L27/11 , G11C11/40 , H01L27/02
CPC分类号： H01L27/1108 , Y10S257/903 , Y10S257/904
摘要： An integrated circuit, illustratively an SRAM, with pull down gates symmetrically positioned with respect to the ground line is disclosed. The symmetric positioning helps to insure cell stability.
摘要翻译：公开了一种集成电路，例如SRAM，具有相对于接地线对称定位的下拉门。对称定位有助于确保细胞稳定性。

6. 发明授权

US5128738A Integrated circuit 失效
标题翻译：集成电路
公开(公告)号：US5128738A
公开(公告)日：1992-07-07
申请号：US701270
申请日：1991-05-16
申请人： Kuo-Hua Lee , William J. Nagy , Janmye Sung
发明人： Kuo-Hua Lee , William J. Nagy , Janmye Sung
IPC分类号： H01L21/8244 , H01L23/528 , H01L27/11
CPC分类号： H01L23/5283 , H01L27/1112 , H01L2924/0002
摘要： A semiconductor memory cell with parallel gates is disclosed. The direction of the gates is desirably chosen to minimize lithographic astigmatic effects. Thus gates of comparatively uniform width are produced and predictability of transistor performance thereby improved. Another embodiment of the invention features a connetion between two conductive layers and a source/drain. The connection forms a node between one access transistor and one pull-down transistor.

7. 发明授权

US5334541A Method of fabricating an integrated circuit with lines of critical width extending in the astigmatically preferred direction of the lithographic tool 失效
标题翻译：制造具有在光刻工具的散光优选方向上延伸的临界宽度线的集成电路的方法
公开(公告)号：US5334541A
公开(公告)日：1994-08-02
申请号：US999731
申请日：1992-12-31
申请人： Thomas E. Adams , Kuo-Hua Lee , William J. Nagy , Janmye Sung
发明人： Thomas E. Adams , Kuo-Hua Lee , William J. Nagy , Janmye Sung
IPC分类号： H01L21/8244 , H01L27/11 , H01L21/285
CPC分类号： H01L27/1112
摘要： A semiconductor memory cell with parallel gates is disclosed. The direction of the gates is desirably chosen to minimize lithographic astigmatic effects. Thus gates of comparatively uniform width are produced and predictability of transistor performance thereby improved. Another embodiment of the invention features a connection between two conductive layers and a source/drain. The connection forms a node between one access transistor and one pull-down transistor.
摘要翻译：公开了一种具有并联栅极的半导体存储单元。期望选择栅极的方向以使光刻散光效应最小化。因此，产生相对均匀宽度的栅极，从而提高了晶体管性能的可预测性。本发明的另一个实施例的特征在于两个导电层和源极/漏极之间的连接。该连接在一个存取晶体管和一个下拉晶体管之间形成一个节点。

8. 发明授权

US5002898A Integrated-circuit device isolation 失效
标题翻译：集成电路器件隔离
公开(公告)号：US5002898A
公开(公告)日：1991-03-26
申请号：US423992
申请日：1989-10-19
申请人： Larry B. Fritzinger , Kuo-Hua Lee , Chih-Yuan Lu , Janmye Sung
发明人： Larry B. Fritzinger , Kuo-Hua Lee , Chih-Yuan Lu , Janmye Sung
IPC分类号： H01L21/76 , H01L21/316 , H01L21/32 , H01L21/762
CPC分类号： H01L21/32 , H01L21/76202
摘要： In the manufacture of integrated-circuit semiconductor devices, prior to formation of a field oxide, a mask structure is provided on a silicon device area, comprising a pad oxide layer, a polysilicon buffer layer, a protective oxide layer, and a silicon nitride mask layer. Inclusion of the protective layer between polysilicon and silicon nitride layers prevents pad oxide failure and attendant substrate etching during strip-etching of the structure overlying the pad oxide.

9. 发明授权

US4935376A Making silicide gate level runners 失效
标题翻译：制作硅化物浇口水平赛跑者
公开(公告)号：US4935376A
公开(公告)日：1990-06-19
申请号：US420207
申请日：1989-10-12
申请人： Steven J. Hillenius , Kuo-Hua Lee , Chih-Yuan Lu , Janmye Sung
发明人： Steven J. Hillenius , Kuo-Hua Lee , Chih-Yuan Lu , Janmye Sung
IPC分类号： H01L29/78 , H01L21/28 , H01L21/3205 , H01L21/336 , H01L21/768
CPC分类号： H01L21/76889 , H01L21/28052 , H01L21/28123
摘要： Integrated circuits are fabricated with thick self-aligned silicide runners on the field oxide by etching back the first dielectric to expose patterned polysilicon on the field oxide and then forming a silicide on the patterned polysilicon.

10. 发明授权

US6137130A Capacitor over bit line structure using a straight bit line shape 有权
标题翻译：使用直线形状的位线结构电容器
公开(公告)号：US6137130A
公开(公告)日：2000-10-24
申请号：US455357
申请日：1999-12-06
申请人： Janmye Sung
发明人： Janmye Sung
IPC分类号： H01L21/8242 , H01L27/108
CPC分类号： H01L27/10852
摘要： A method of creating a capacitor over bit line structure, used for high density, DRAM designs, has been developed. The process consists of creating a straight bit line shape, connected to an underlying polysilicon contact plug structure, which in turn contacts an underlying source and drain region. A storage node contact hole is opened through insulator layers and through the straight bit line shape. After passivation of the storage node contact hole with silicon nitride spacers, a storage node structure is formed on an overlying insulator layer, as well as in the storage node contact hole, overlying and contacting another polysilicon contact plug.
摘要翻译：已经开发了用于高密度DRAM设计的位线结构上产生电容器的方法。该过程包括产生直的位线形状，连接到下面的多晶硅接触插塞结构，其又接触下面的源极和漏极区域。存储节点接触孔通过绝缘体层和直的位线形状打开。在用氮化硅间隔物钝化存储节点接触孔之后，在覆盖的绝缘体层以及存储节点接触孔中形成存储节点结构，覆盖并接触另一个多晶硅接触插塞。

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