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    • 9. 发明授权
    • Multifunctional adjustable ladder assembly
    • 多功能可调梯组件
    • US06880675B2
    • 2005-04-19
    • US10423607
    • 2003-04-25
    • Kuo-Ching Huang
    • Kuo-Ching Huang
    • E06C1/18E06C1/22E06C7/08E06C1/00
    • E06C7/083E06C1/18E06C1/22
    • A ladder assembly includes two symmetric support stands pivotally connected with each other. Each of the two support stands includes a main frame, an upper frame, a lower frame, a top bar, a retraction control unit, and four fixing devices. Thus, height of the ladder assembly can be adjusted easily and conveniently, thereby facilitating the user operating the ladder assembly. In addition, the upper frame and the lower frame can be folded on the main frame, so as to reduce the volume the ladder assembly efficiently, thereby greatly facilitating storage and transportation of the ladder assembly.
    • 梯子组件包括彼此枢转连接的两个对称支撑架。 两个支撑台中的每一个包括主框架,上框架,下框架,顶杆,缩回控制单元和四个固定装置。 因此,可以容易且方便地调整梯子组件的高度,从而便于使用者操作梯子组件。 此外,上框架和下框架可以折叠在主框架上,以便有效地减少梯子组件的体积,从而极大地方便了梯子组件的存储和运输。
    • 10. 发明授权
    • One-transistor RAM approach for high density memory application
    • 用于高密度存储器应用的单晶体管RAM方法
    • US06661043B1
    • 2003-12-09
    • US10400401
    • 2003-03-27
    • Kuo-Ching HuangWen-Cheng ChenWen-Chuan ChiangKuo-Chuang Tseng
    • Kuo-Ching HuangWen-Cheng ChenWen-Chuan ChiangKuo-Chuang Tseng
    • H01L218242
    • H01L27/1085H01L27/1087
    • A new method is provided for the creation of a 1T RAM cell. Standard processing is applied to create STI trenches in the surface of a substrate, N2 implantations are performed into the sidewalls of the STI trenches. A layer of lining oxide is created, the implanted N2 interacts with the lining oxide to form SiON over exposed surfaces of the STI trenches. STI oxide is deposited and polished, filling the STI trenches there-with. Crown patterning is performed to define capacitor areas, the crown patterning stops on a layer of etch stop material and the created SION and partially removes STI oxide from the STI trenches. Layers of etch stop material, exposed SiON and pad oxide are removed, exposing the surface of the silicon substrate, the etched layers of STI oxide are not affected by this removal. A layer of SAC oxide is grown, n-well and p-well implantations are performed into the surface of the substrate. The layer of SAC oxide is removed, gate oxide is grown, polysilicon is deposited and patterned and etched, forming polysilicon gate material and polysilicon top plate of the capacitor. Standard processing is further applied to complete the 1T-RAM cell by providing gate spacers and impurity implantations for the gate electrode, by saliciding contact surfaces and by providing contacts to the points of contact of the cell.
    • 提供了一种用于创建1T RAM单元的新方法。 施加标准处理以在衬底的表面中产生STI沟槽,在STI沟槽的侧壁中进行N2注入。 产生衬里氧化层,注入的N 2与衬里氧化物相互作用以在STI沟槽的暴露表面上形成SiON。 沉积和抛光STI氧化物,在那里填充STI沟槽。 进行冠图案化以限定电容器区域,冠图案停止在蚀刻停止材料层上,并且所产生的SION并且部分地从STI沟槽去除STI氧化物。 蚀刻停止材料层,暴露的SiON和衬垫氧化物层被去除,暴露硅衬底的表面,STI氧化物的蚀刻层不受该去除的影响。 生长一层SAC氧化物,n阱和p阱注入进行到衬底的表面。 去除SAC氧化物层,生长栅极氧化物,沉积多晶硅并进行图案化和蚀刻,形成电容器的多晶硅栅极材料和多晶硅顶板。 进一步应用标准处理,通过为栅电极提供栅极间隔物和杂质注入,通过对接触表面进行喷淋并且通过提供与电池的接触点的接触来完成1T-RAM单元。