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1. 发明授权

US07391083B2 Semiconductor device and a method of manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US07391083B2
公开(公告)日：2008-06-24
申请号：US11405540
申请日：2006-04-18
申请人： Kunihiko Kato , Masami Koketsu , Shigeya Toyokawa , Keiichi Yoshizumi , Hideki Yasuoka , Yasuhiro Takeda
发明人： Kunihiko Kato , Masami Koketsu , Shigeya Toyokawa , Keiichi Yoshizumi , Hideki Yasuoka , Yasuhiro Takeda
IPC分类号： H01L23/62
CPC分类号： H01L21/823857 , H01L21/823814 , H01L21/823878 , H01L27/0629 , H01L28/40
摘要： A method of manufacturing a semiconductor integrated circuit device having on the same substrate both a high breakdown voltage MISFET and a low breakdown voltage MISFET is provided. An element isolation trench is formed in advance so that the width thereof is larger than the sum of the thickness of a polycrystalline silicon film serving as a gate electrode of a low breakdown voltage, the thickness of a gate insulating film and an alignment allowance in processing of a gate electrode in a direction orthogonal to the extending direction of the gate electrode and is larger than the thickness of the polycrystalline silicon film in a planar region not overlapping the gate electrode. It is possible to decrease the number of manufacturing steps for the semiconductor integrated circuit device.
摘要翻译：提供一种制造半导体集成电路器件的方法，所述半导体集成电路器件在同一衬底上具有高击穿电压MISFET和低击穿电压MISFET。预先形成元件隔离沟槽，使得其宽度大于用作低击穿电压的栅电极的多晶硅膜的厚度，栅绝缘膜的厚度和处理中的对准余量之和在与栅电极的延伸方向正交的方向上的栅电极大于不与栅电极重叠的平面区域中的多晶硅膜的厚度。可以减少半导体集成电路器件的制造步骤的数量。

2. 发明授权

US07514749B2 Semiconductor device and a method of manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US07514749B2
公开(公告)日：2009-04-07
申请号：US12122717
申请日：2008-05-18
申请人： Kunihiko Kato , Masami Koketsu , Shigeya Toyokawa , Keiichi Yoshizumi , Hideki Yasuoka , Yasuhiro Takeda
发明人： Kunihiko Kato , Masami Koketsu , Shigeya Toyokawa , Keiichi Yoshizumi , Hideki Yasuoka , Yasuhiro Takeda
IPC分类号： H01L23/62
CPC分类号： H01L21/823857 , H01L21/823814 , H01L21/823878 , H01L27/0629 , H01L28/40
摘要： A method of manufacturing a semiconductor integrated circuit device having on the same substrate both a high breakdown voltage MISFET and a low breakdown voltage MISFET is provided. An element isolation trench is formed in advance so that the width thereof is larger than the sum of the thickness of a polycrystalline silicon film serving as a gate electrode of a low breakdown voltage, the thickness of a gate insulating film and an alignment allowance in processing of a gate electrode in a direction orthogonal to the extending direction of the gate electrode and is larger than the thickness of the polycrystalline silicon film in a planar region not overlapping the gate electrode. It is possible to decrease the number of manufacturing steps for the semiconductor integrated circuit device.
摘要翻译：提供一种制造半导体集成电路器件的方法，该半导体集成电路器件在相同的衬底上具有高击穿电压MISFET和低击穿电压MISFET。预先形成元件隔离沟槽，使得其宽度大于用作低击穿电压的栅电极的多晶硅膜的厚度，栅绝缘膜的厚度和处理中的对准余量之和在与栅电极的延伸方向正交的方向上的栅电极大于不与栅电极重叠的平面区域中的多晶硅膜的厚度。可以减少半导体集成电路器件的制造步骤的数量。

3. 发明申请

US20060237795A1 Semiconductor device and a method of manufacturing the same 有权
公开(公告)号：US20060237795A1
公开(公告)日：2006-10-26
申请号：US11405540
申请日：2006-04-18
申请人： Kunihiko Kato , Masami Koketsu , Shigeya Toyokawa , Keiichi Yoshizumi , Hideki Yasuoka , Yasuhiro Takeda
发明人： Kunihiko Kato , Masami Koketsu , Shigeya Toyokawa , Keiichi Yoshizumi , Hideki Yasuoka , Yasuhiro Takeda
IPC分类号： H01L23/62
CPC分类号： H01L21/823857 , H01L21/823814 , H01L21/823878 , H01L27/0629 , H01L28/40
摘要： A method of manufacturing a semiconductor integrated circuit device having on the same substrate both a high breakdown voltage MISFET and a low breakdown voltage MISFET is provided. An element isolation trench is formed in advance so that the width thereof is larger than the sum of the thickness of a polycrystalline silicon film serving as a gate electrode of a low breakdown voltage, the thickness of a gate insulating film and an alignment allowance in processing of a gate electrode in a direction orthogonal to the extending direction of the gate electrode and is larger than the thickness of the polycrystalline silicon film in a planar region not overlapping the gate electrode. It is possible to decrease the number of manufacturing steps for the semiconductor integrated circuit device.

4. 发明授权

US08604583B2 Semiconductor device comprising a Schottky barrier diode 有权
标题翻译：包括肖特基势垒二极管的半导体器件
公开(公告)号：US08604583B2
公开(公告)日：2013-12-10
申请号：US13438190
申请日：2012-04-03
申请人： Kunihiko Kato , Hideki Yasuoka , Masatoshi Taya , Masami Koketsu
发明人： Kunihiko Kato , Hideki Yasuoka , Masatoshi Taya , Masami Koketsu
IPC分类号： H01L29/66
CPC分类号： H01L29/872 , H01L27/0629 , H01L29/0692 , H01L29/417
摘要： The present invention aims to enhance the reliability of a semiconductor device equipped with a Schottky barrier diode within the same chip, and its manufacturing technology. The semiconductor device includes an n-type n-well region formed over a p-type semiconductor substrate, an n-type cathode region formed in part thereof and higher in impurity concentration than the n-well region, a p-type guard ring region formed so as to surround the n-type cathode region, an anode conductor film formed so as to integrally cover the n-type cathode region and the p-type guard ring region and to be electrically coupled thereto, n-type cathode conduction regions formed outside the p-type guard ring region with each separation portion left therebetween, and a cathode conductor film formed so as to cover the n-type cathode conduction regions and to be electrically coupled thereto. The anode conductor film and the n-type cathode region are Schottky-coupled to each other.
摘要翻译：本发明旨在提高在同一芯片内配备肖特基势垒二极管的半导体器件及其制造技术的可靠性。半导体器件包括在p型半导体衬底上形成的n型n阱区，部分形成并且杂质浓度高于n阱区的n型阴极区，p型保护环区形成为包围n型阴极区域的阳极导体膜，形成为一体地覆盖n型阴极区域和p型保护环区域并与其电耦合，形成n型阴极导电区域在其间留有各个分离部分的p型保护环区域外部，以及形成为覆盖n型阴极导电区域并与其电耦合的阴极导体膜。阳极导体膜和n型阴极区彼此肖特基耦合。

5. 发明授权

US08169047B2 Semiconductor device comprising a schottky barrier diode 有权
标题翻译：包括肖特基势垒二极管的半导体器件
公开(公告)号：US08169047B2
公开(公告)日：2012-05-01
申请号：US12205622
申请日：2008-09-05
申请人： Kunihiko Kato , Hideki Yasuoka , Masatoshi Taya , Masami Koketsu
发明人： Kunihiko Kato , Hideki Yasuoka , Masatoshi Taya , Masami Koketsu
IPC分类号： H01L29/66
CPC分类号： H01L29/872 , H01L27/0629 , H01L29/0692 , H01L29/417
摘要： The present invention aims to enhance the reliability of a semiconductor device equipped with a Schottky barrier diode within the same chip, and its manufacturing technology. The semiconductor device includes an n-type n-well region formed over a p-type semiconductor substrate, an n-type cathode region formed in part thereof and higher in impurity concentration than the n-well region, a p-type guard ring region formed so as to surround the n-type cathode region, an anode conductor film formed so as to integrally cover the n-type cathode region and the p-type guard ring region and to be electrically coupled thereto, n-type cathode conduction regions formed outside the p-type guard ring region with each separation portion left therebetween, and a cathode conductor film formed so as to cover the n-type cathode conduction regions and to be electrically coupled thereto. The anode conductor film and the n-type cathode region are Schottky-coupled to each other.
摘要翻译：本发明旨在提高在同一芯片内配备肖特基势垒二极管的半导体器件及其制造技术的可靠性。半导体器件包括在p型半导体衬底上形成的n型n阱区，部分形成并且杂质浓度高于n阱区的n型阴极区，p型保护环区形成为包围n型阴极区域的阳极导体膜，形成为一体地覆盖n型阴极区域和p型保护环区域并与其电耦合，形成n型阴极导电区域在其间留有各个分离部分的p型保护环区域外部，以及形成为覆盖n型阴极导电区域并与其电耦合的阴极导体膜。阳极导体膜和n型阴极区彼此肖特基耦合。

6. 发明授权

US08222712B2 Semiconductor integrated circuit device and a method of manufacturing the same 有权
标题翻译：半导体集成电路器件及其制造方法
公开(公告)号：US08222712B2
公开(公告)日：2012-07-17
申请号：US12399957
申请日：2009-03-08
申请人： Kunihiko Kato , Shigeya Toyokawa , Kozo Watanabe , Masatoshi Taya
发明人： Kunihiko Kato , Shigeya Toyokawa , Kozo Watanabe , Masatoshi Taya
IPC分类号： H01L29/872
CPC分类号： H01L29/872 , H01L21/823857 , H01L21/823878 , H01L27/0629 , H01L29/0619 , H01L29/417 , H01L2924/0002 , H01L2924/00
摘要： To achieve a further reduction in the size of a finished product by reducing the number of externally embedded parts, the embedding of a Schottky barrier diode which is relatively large in the amount of current in a semiconductor integrated circuit device has been pursued. In such a case, it is general practice to densely arrange a large number of contact electrodes in a matrix over a Schottky junction region. It has been widely performed to perform a sputter etching process with respect to the surface of a silicide layer at the bottom of each contact hole before a barrier metal layer is deposited. However, in a structure in which electrodes are thus arranged over a Schottky junction region, a reverse leakage current in a Schottky barrier diode is varied by variations in the amount of sputter etching. The present invention is a semiconductor integrated circuit device having a Schottky barrier diode in which contact electrodes are arranged over a guard ring in contact with a peripheral isolation region.
摘要翻译：为了通过减少外部嵌入部件的数量来进一步减小成品的尺寸，已经追求了在半导体集成电路器件中嵌入的电流量相对较大的肖特基势垒二极管。在这种情况下，通常的做法是在肖特基结区域上将矩阵中的大量接触电极密集布置。在阻挡金属层沉积之前，已经广泛地执行相对于每个接触孔底部的硅化物层的表面的溅射蚀刻工艺。然而，在其中将电极布置在肖特基结区上方的结构中，肖特基势垒二极管中的反向泄漏电流由于溅射蚀刻量的变化而变化。本发明是一种具有肖特基势垒二极管的半导体集成电路器件，其中接触电极布置在与周边隔离区接触的保护环上。

7. 发明授权

US08546905B2 Semiconductor integrated circuit device and a method of manufacturing the same 有权
标题翻译：半导体集成电路器件及其制造方法
公开(公告)号：US08546905B2
公开(公告)日：2013-10-01
申请号：US13371015
申请日：2012-02-10
申请人： Kunihiko Kato , Shigeya Toyokawa , Kozo Watanabe , Masatoshi Taya
发明人： Kunihiko Kato , Shigeya Toyokawa , Kozo Watanabe , Masatoshi Taya
IPC分类号： H01L29/872
CPC分类号： H01L29/872 , H01L21/823857 , H01L21/823878 , H01L27/0629 , H01L29/0619 , H01L29/417 , H01L2924/0002 , H01L2924/00
摘要： To reduce size of a finished product by reducing the number of externally embedded parts, embedding of a Schottky barrier diode relatively large in the amount of current in a semiconductor integrated circuit device has been pursued. It is general practice to densely arrange a number of contact electrodes in a matrix over a Schottky junction region. A sputter etching process to the surface of a silicide layer at the bottom of each contact hole is performed before a barrier metal layer is deposited. However, in a structure in which electrodes are thus arranged over a Schottky junction region, a reverse leakage current in a Schottky barrier diode is varied by variations in the amount of sputter etching. The present invention is a semiconductor integrated circuit device having a Schottky barrier diode in which contact electrodes are arranged over a guard ring in contact with a peripheral isolation region.
摘要翻译：为了通过减少外部嵌入部件的数量来减小成品的尺寸，已经追求了在半导体集成电路器件中嵌入相当大的电流量的肖特基势垒二极管。通常的做法是在肖特基结区域上的矩阵中密集布置多个接触电极。在沉积阻挡金属层之前，对每个接触孔底部的硅化物层的表面进行溅射蚀刻工艺。然而，在其中将电极布置在肖特基结区上方的结构中，肖特基势垒二极管中的反向泄漏电流由于溅射蚀刻量的变化而变化。本发明是一种具有肖特基势垒二极管的半导体集成电路器件，其中接触电极布置在与周边隔离区接触的保护环上。

8. 发明授权

US4504875A Information scanning circuit for use with a detachable portable _cassette tape recorder 失效
标题翻译：用于可拆卸便携式盒式磁带录像机的信息扫描电路
公开(公告)号：US4504875A
公开(公告)日：1985-03-12
申请号：US471216
申请日：1983-03-01
申请人： Kunihiko Kato , Akihiko Murahashi
发明人： Kunihiko Kato , Akihiko Murahashi
IPC分类号： H04B1/20 , G11B15/02 , G11B15/087 , G11B15/10 , G11B25/06 , G11B27/22 , G11B31/00 , G11B33/06 , G11B33/12
CPC分类号： G11B15/103 , G11B25/063 , G11B27/22 , G11B31/00 , G11B31/003 , G11B33/122
摘要： A cassette tape recorder (1) of pocket size, which is detachably coupled to a radio receiver (2) is given music searching function. The cassette tape recorder (1) is normally powered by small capacity cells (B1) when used by itself, and is powered by a large capacity power source (B2) included in the radio (2). A reproducing signal derived from a reproduce head (9) is fed to a solenoid control circuit (14) built in the radio (2) to detect a no-signal portion between two consecutive music pieces. When such a no-signal portion is detected during music search with fast playback, a solenoid driving signal is fed to a solenoid (12) built in the tape recorder (1) to terminate fast playback and put the tape recorder (1) in a normal playback mode. A switch (S1) arranged to be automatically switched when the tape recorder (1) engages the radio (2) is provided to automatically select the small or large capacity power source (B1 or B2).
摘要翻译：具有可拆卸地耦合到无线电接收器（2）的口袋尺寸的盒式磁带录音机（1）被给予音乐搜索功能。盒式磁带录像机（1）通常由小容量电池（B1）供电，并且由包括在无线电（2）中的大容量电源（B2）供电。从再现头（9）导出的再现信号被馈送到内置在无线电（2）中的螺线管控制电路（14），以检测两个连续音乐片段之间的无信号部分。当在快速重放的音乐搜索期间检测到这样的无信号部分时，将螺线管驱动信号馈送到内置在磁带录像机（1）中的螺线管（12）以终止快速重放，并将磁带录音机（1）放入普通播放模式。提供当磁带录像机（1）接合无线电（2）时被自动切换的开关（S1），以自动选择小容量或大容量电源（B1或B2）。

9. 发明申请

US20080042685A1 INPUT AND OUTPUT CIRCUIT 失效
标题翻译：输入和输出电路
公开(公告)号：US20080042685A1
公开(公告)日：2008-02-21
申请号：US11839668
申请日：2007-08-16
申请人： Kunihiko Kato
发明人： Kunihiko Kato
IPC分类号： H03K19/0185 , G11C7/10 , H03K19/0175
CPC分类号： G11C29/02 , G11C7/1051 , G11C7/1057 , G11C7/1078 , G11C7/1084 , G11C29/022
摘要： Stable testing is performed on an input and output circuit. An output stage outputting output signal to input/output terminal DQ comprises: a differential pair formed from an Nch transistor N1, having as load a Pch transistor P1 and resistance element R1, and an Nch transistor N2, having as load a Pch transistor P2 and resistance element R2; and an Nch transistor N3 supplying operating current to the differential pair. The input/output terminal DQ is connected to the drain of the Nch transistor N1. The output stage is operated as differential pair, in the normal operation mode (TM=L), wherein the Pch transistors P1, P2 are ON, a read-data signal RD is supplied to the differential pair, and a specified voltage CC is supplied to the gate of the Nch transistor N3; and in the test mode (TM=H), a CMOS circuit is established wherein a read-data signal RD is supplied to the gate of the Pch transistor P1 and the gate of the Nch transistor N3, turning the Nch transistor N1 ON.
摘要翻译：在输入和输出电路上执行稳定的测试。向输入/输出端子DQ输出输出信号的输出级包括：由负载为Pch晶体管P 1和电阻元件R 1的N沟道晶体管N 1和Nch晶体管N 2形成的差分对，其具有负载a Pch晶体管P 2和电阻元件R 2; 以及向差分对提供工作电流的N沟道晶体管N 3。输入/输出端子DQ连接到N沟道晶体管N 1的漏极。在正常工作模式（TM = L）中，输出级作为差分对工作，其中Pch晶体管P 1，P 2导通，读数据信号RD被提供给差分对，并且指定的电压CC 被提供给N沟道晶体管N 3的栅极; 并且在测试模式（TM = H）中，建立CMOS电路，其中将读数据信号RD提供给Pch晶体管P 1的栅极和Nch晶体管N 3的栅极，使Nch晶体管N 1 上。

10. 发明授权

US5951692A Single-chip memory system having a redundancy judging circuit 失效
标题翻译：具有冗余判定电路的单片存储器系统
公开(公告)号：US5951692A
公开(公告)日：1999-09-14
申请号：US788249
申请日：1997-01-27
申请人： Kunihiko Kato
发明人： Kunihiko Kato
IPC分类号： G11C11/413 , G11C11/401 , G11C29/00 , G11C29/04 , G06F11/00
CPC分类号： G11C29/78
摘要： To use both an array of main memory cells and an array of redundant memory cells efficiently during a block writing operation, a memory system for performing the block writing operation includes a bit line activator activating at least one bit line of bit lines of the array of main memory cells and at least one bit line of bit lines of the array of redundant memory cells simultaneously during the block writing operation.
摘要翻译：为了在块写入操作期间有效地使用主存储单元阵列和冗余存储单元阵列，用于执行块写入操作的存储器系统包括位线激活器激活阵列的位线的至少一个位线主存储单元和冗余存储单元阵列的位线的至少一位位线在块写入操作期间同时进行。

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