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1. 发明授权

US4704600A Oversampling converter 失效
标题翻译：过采样转换器
公开(公告)号：US4704600A
公开(公告)日：1987-11-03
申请号：US826128
申请日：1986-02-04
申请人： Kuniharu Uchimura , Tsutomu Kobayashi , Atushi Iwata , Toshio Hayashi , Tadakatsu Kumura
发明人： Kuniharu Uchimura , Tsutomu Kobayashi , Atushi Iwata , Toshio Hayashi , Tadakatsu Kumura
IPC分类号： H03M1/12 , H03M1/66 , H03M3/02 , H03M3/00
CPC分类号： H03M3/418 , H03M7/3022
摘要： An oversampling converter includes first and second integrators for integrating a difference between an input terminal voltage and feedback voltages, first and second quantizers for quantizing outputs from the first and second integrators, respectively, first and second feedback paths for feeding back as the feedback voltages outputs from the first quantizer to the input sides of the first and second integrators, a differentiator arranged at an output side of the second quantizer, an adder for adding an output from the differentiator and the output from the first quantizer, and a circuit for supplying an output from the first integrator to an input terminal of the second integrator. Two or more quantization loops may be used. When the oversampling converter is used as an A/D converter, A/D converters are arranged in the first and second feedback paths. When the oversampling converter is used as a D/A converter, D/A converters are arranged between the adder and the first quantizer and between the adder and the second quantizer.
摘要翻译：过采样转换器包括用于积分输入端电压和反馈电压之间的差的第一和第二积分器，分别用于量化来自第一和第二积分器的输出的第一和第二量化器，用于反馈的第一和第二反馈路径作为反馈电压输出从第一量化器到第二积分器的输入侧，布置在第二量化器的输出侧的微分器，用于将来自微分器的输出和来自第一量化器的输出相加的加法器，以及用于提供从第一积分器输出到第二积分器的输入端。可以使用两个或更多个量化循环。当过采样转换器用作A / D转换器时，A / D转换器被布置在第一和第二反馈路径中。当过采样转换器用作D / A转换器时，D / A转换器被布置在加法器和第一量化器之间以及加法器和第二量化器之间。

2. 发明授权

US4622480A Switched capacitor circuit with high power supply projection ratio 失效
标题翻译：开关电容电路具有高电源投影比
公开(公告)号：US4622480A
公开(公告)日：1986-11-11
申请号：US487523
申请日：1983-04-22
申请人： Kuniharu Uchimura , Atushi Iwata
发明人： Kuniharu Uchimura , Atushi Iwata
IPC分类号： G11C27/02 , H03H19/00 , G05F5/00
CPC分类号： H03H19/00 , G11C27/024 , G11C27/026
摘要： In a switched capacitor circuit, in order to eliminate leakage of a power supply noise component to a signal line through an input capacitance of an operation amplifier, (1) an operating current of at least a first, differential stage among stages of the operational amplifier is regulated by a current regulation bias circuit, and (2) a power supply noise component having the same phase as that of an input signal is applied to the gate of a transistor of a gain stage, thereby stabilizing the operating point. In order to eliminate leakage of the power supply noise component to the signal line through a parasitic capacitance of an analog switch, (3) a dummy switch is used to detect a signal corresponding to the leakage component of the power supply noise component to the signal line, and an inverted signal having the opposite phase to that of the signal corresponding to the leakage component is applied to a substrate of the analog switch, thereby cancelling the actual leakage component.

3. 发明授权

US5630024A Method and apparatus for processing using neural network with reduced calculation amount 失效
标题翻译：使用神经网络处理减少计算量的方法和装置
公开(公告)号：US5630024A
公开(公告)日：1997-05-13
申请号：US373440
申请日：1995-01-17
申请人： Kimihisa Aihara , Kuniharu Uchimura
发明人： Kimihisa Aihara , Kuniharu Uchimura
IPC分类号： G06N3/04 , G06N3/063 , G06F15/18
CPC分类号： G06N3/063 , G06N3/0481
摘要： A neural network circuit and a processing scheme using the neural network circuit in which a synapse calculation for each input value and a corresponding synapse weight of each input value which are expressed by binary bit sequences is carried out by using a sequentially specified bit of the corresponding synapse weight, a summation calculation for sequentially summing synapse calculation results for the input values is carried out to obtain a summation value, a prescribed nonlinear processing is applied to the obtained summation value so as to determine the output value, whether the obtained summation value reached to a saturation region of a transfer characteristic of the prescribed nonlinear processing is judged, the synapse calculation and the summation calculation are controlled to sequentially carry out the synapse calculation from upper bits of the corresponding synapse weight, and to stop the synapse calculation and the summation calculation whenever it is judged that the obtained summation value reached to the saturation region.
摘要翻译：神经网络电路和使用神经网络电路的处理方案，其中通过二进制位序列表示的每个输入值的每个输入值和对应的突触权重的突触计算通过使用相应的突变权重，进行用于顺序求和输入值的突触计算结果的求和计算以获得求和值，对获得的求和值应用规定的非线性处理，以确定输出值，获得的求和值是否达到判断为规定的非线性处理的传递特性的饱和区域，控制突触计算和求和计算，以依次对相应的突触重量的高位进行突触计算，并停止突触计算和求和计算每当判断为obtai ned求和值达到饱和区。

4. 发明授权

US5353383A Neural network circuit 失效
标题翻译：神经网络电路
公开(公告)号：US5353383A
公开(公告)日：1994-10-04
申请号：US909993
申请日：1992-07-07
申请人： Kuniharu Uchimura , Osamu Saito , Yoshihito Amemiya , Atsushi Iwata
发明人： Kuniharu Uchimura , Osamu Saito , Yoshihito Amemiya , Atsushi Iwata
IPC分类号： G06N3/063 , G06F15/18
CPC分类号： G06K9/6287 , G06N3/063
摘要： A neural network circuit including a number n of weight coefficients (W1-Wn) corresponding to a number n of inputs, subtraction circuits for determining the difference between inputs and the weight coefficients in each input terminal, the result thereof being inputted into absolute value circuits, all calculation results of the absolute value circuits corresponding to the inputs and the weight coefficients being inputted into an addition circuit and accumulated, and this accumulation result determining the output value. A threshold value circuit determines the final output value, according to a step function pattern, a polygonal line pattern, or a sigmoid function pattern, depending on the object. In the case in which a neural network circuit is realized by means of digital circuits, the absolute value circuits can include simply EX-OR logic (exclusive OR) gates. Furthermore, in the case in which the input terminals have two input paths and two weight coefficients corresponding to each input path, the neuron circuits form a recognition area having a flexible shape which is controlled by the weight coefficients.
摘要翻译：包含对应于n个输入的权重系数（W1-Wn）数量n的神经网络电路，用于确定输入端之间的差异和每个输入端子的权重系数的减法电路，其结果被输入到绝对值电路将与输入对应的绝对值电路和加权系数的所有计算结果输入加法电路并累加，并且该累加结果确定输出值。根据对象，阈值电路根据阶梯函数图案，折线图案或S形函数图案确定最终输出值。在通过数字电路实现神经网络电路的情况下，绝对值电路可以包括简单的EX-OR逻辑（异或）门。此外，在输入端子具有两个输入路径和对应于每个输入路径的两个权重系数的情况下，神经元电路形成具有由权重系数控制的柔性形状的识别区域。

5. 发明授权

US5467429A Neural network circuit 失效
标题翻译：神经网络电路
公开(公告)号：US5467429A
公开(公告)日：1995-11-14
申请号：US266691
申请日：1994-06-28
申请人： Kuniharu Uchimura , Osamu Saito , Yoshihito Amemiya , Atsushi Iwata
发明人： Kuniharu Uchimura , Osamu Saito , Yoshihito Amemiya , Atsushi Iwata
IPC分类号： G06N3/063 , G06F15/18
CPC分类号： G06K9/6287 , G06N3/063
摘要： A neural network circuit including a number n of weight coefficients (W1-Wn) corresponding to a number n of inputs, subtraction circuits for determining the difference between inputs and the weight coefficients in each input terminal, the result thereof being inputted into absolute value circuits, all calculation results of the absolute value circuits corresponding to the inputs and the weight coefficients being inputted into an addition circuit and accumulated, and this accumulation result determining the output valve. A threshold valve circuit determines the final output value, according to a step function pattern, a polygonal line pattern, or a sigmoid function pattern, depending on the object. In the case in which a neural network circuit is realized by means of digital circuits, the absolute value circuits can include simply EX-OR logic (exclusive OR) gates. Furthermore, in the case in which the input terminals have two input paths and two weight coefficients corresponding to each input path, the neuron circuits form a recognition area having a flexible shape which is controlled by the weight coefficients.
摘要翻译：包含对应于n个输入的权重系数（W1-Wn）数量n的神经网络电路，用于确定输入端之间的差异和每个输入端子的权重系数的减法电路，其结果被输入到绝对值电路对应于输入和加权系数的绝对值电路的所有计算结果被输入到加法电路并累积，并且该累加结果确定输出阀。阈值阀电路根据步骤功能图案，多边形线图案或S形函数图案来确定最终输出值，这取决于对象。在通过数字电路实现神经网络电路的情况下，绝对值电路可以包括简单的EX-OR逻辑（异或）门。此外，在输入端子具有两个输入路径和对应于每个输入路径的两个权重系数的情况下，神经元电路形成具有由权重系数控制的柔性形状的识别区域。

6. 发明授权

US5166539A Neural network circuit 失效
标题翻译：神经网络电路
公开(公告)号：US5166539A
公开(公告)日：1992-11-24
申请号：US727065
申请日：1991-07-08
申请人： Kuniharu Uchimura , Osamu Saito , Yoshihito Amemiya , Atsushi Iwata
发明人： Kuniharu Uchimura , Osamu Saito , Yoshihito Amemiya , Atsushi Iwata
IPC分类号： G06N3/063
CPC分类号： G06K9/6287 , G06N3/063
摘要： A neural network circuit, in which a number n of weight coefficients (Wl-wn) corresponding to a number n of inputs are provided, subtraction circuits determine the difference between inputs and the weight coefficients in each input terminal, the result thereof is inputted into absolute value circuits, all calculation results of the absolute value circuts corresponding to the inputs and the weight coefficients are inputted into an addition circuit and accumulated, and this accumulation result determines the output value. The threshold value circuit, which determines the final output value, has characteristics of a step function pattern, a polygonal line pattern, or a sigmoid function pattern, depending on the object. In the case in which a neural network circuit is realized by means of digital circuits, the absolute value circuits can comprise simply EX-OR logic (exclusive OR) gates. Furthermore, in the case in which the input terminals have two input paths and two weight coefficients corresponding to each input path, the neuron circuits form a recognition area having a flexible shape which is controlled by the weight coefficients. Neuron circuits are widely used in pattern recognition; neuron circuits react to a pattern inputted into the input layer and recognition is thereby conducted.

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