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1. 发明申请

US20050110120A1 Scribe line structure of wafer 审中-公开
标题翻译：晶片划线结构
公开(公告)号：US20050110120A1
公开(公告)日：2005-05-26
申请号：US10707222
申请日：2003-11-27
申请人： Kun-Chih Wang , Paul Chen , Jui-Meng Jao , Chien-Li Kuo
发明人： Kun-Chih Wang , Paul Chen , Jui-Meng Jao , Chien-Li Kuo
IPC分类号： H01L21/301 , H01L21/78 , H01L23/544 , H01L23/58 , H01L29/06
CPC分类号： H01L22/34 , H01L21/78 , H01L23/585 , H01L2924/0002 , H01L2924/00
摘要： A wafer scribe line structure is provided. A plurality of lump patterns is set up to fill the entire scribe line area so that the amount of stress the wafer is subjected to during a dicing process is reduced, thereby reducing the probability of having a delamination at the interface of wafer layers. Moreover, the lump patterns can be formed simultaneously with metal interconnects in a metal interconnect process.
摘要翻译：提供晶片划线结构。设置多个块状图案以填充整个划线区域，使得在切割处理期间晶片受到的应力量减小，从而降低在晶片层的界面处发生分层的可能性。此外，块状图案可以在金属互连工艺中与金属互连同时形成。

2. 发明授权

US07026234B2 Parasitic capacitance-preventing dummy solder bump structure and method of making the same 有权
标题翻译：寄生电容防止假焊料凸块结构及其制造方法
公开(公告)号：US07026234B2
公开(公告)日：2006-04-11
申请号：US10709940
申请日：2004-06-08
申请人： Jui-Meng Jao , Shing-Ren Sheu , Kuo-Ming Chen , Hung-Min Liu , Kun-Chih Wang
发明人： Jui-Meng Jao , Shing-Ren Sheu , Kuo-Ming Chen , Hung-Min Liu , Kun-Chih Wang
IPC分类号： H01L21/44 , H01L29/40
CPC分类号： H01L24/13 , H01L23/5222 , H01L24/11 , H01L2224/05001 , H01L2224/05023 , H01L2224/05026 , H01L2224/0508 , H01L2224/05184 , H01L2224/05568 , H01L2224/056 , H01L2224/13099 , H01L2224/131 , H01L2924/0001 , H01L2924/01013 , H01L2924/01022 , H01L2924/01029 , H01L2924/01033 , H01L2924/01074 , H01L2924/01082 , H01L2924/014 , H01L2924/04941 , H01L2924/30105 , H01L2924/00014 , H01L2224/05124 , H01L2224/05147 , H01L2224/05166
摘要： A parasitic capacitance-preventing dummy solder bump structure on a substrate has at least one conductive layer formed on the substrate, a dielectric layer employed to cover the conductive layer, an under bump metallurgy layer (UBM layer) formed on the dielectric layer, and a solder bump formed on the UBM layer.
摘要翻译：衬底上的寄生电容防止虚拟焊料凸块结构具有至少一个形成在衬底上的导电层，用于覆盖导电层的电介质层，形成在电介质层上的凸块下金属层（UBM层）和焊料凸块形成在UBM层上。

3. 发明申请

US20060065976A1 METHOD FOR MANUFACTURING WAFER LEVEL CHIP SCALE PACKAGE STRUCTURE 有权
标题翻译：制造水平流片尺寸包装结构的方法
公开(公告)号：US20060065976A1
公开(公告)日：2006-03-30
申请号：US10711536
申请日：2004-09-24
申请人： Min-Chih Hsuan , Paul Chen , Hermen Liu , Kun-Chih Wang , Kai-Kuang Ho
发明人： Min-Chih Hsuan , Paul Chen , Hermen Liu , Kun-Chih Wang , Kai-Kuang Ho
IPC分类号： H01L23/48
CPC分类号： H01L24/97 , H01L23/15 , H01L23/3114 , H01L23/3128 , H01L23/49816 , H01L24/48 , H01L24/73 , H01L24/81 , H01L24/83 , H01L2224/05001 , H01L2224/05026 , H01L2224/05568 , H01L2224/05644 , H01L2224/05647 , H01L2224/05655 , H01L2224/05664 , H01L2224/05666 , H01L2224/13111 , H01L2224/16225 , H01L2224/2929 , H01L2224/293 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/48465 , H01L2224/73265 , H01L2224/8121 , H01L2224/81815 , H01L2224/97 , H01L2924/00011 , H01L2924/00014 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/01049 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01322 , H01L2924/09701 , H01L2924/10253 , H01L2924/15311 , H01L2924/181 , H01L2924/351 , H01L2224/81 , H01L2924/00 , H01L2924/00012 , H01L2224/29075 , H01L2224/83851 , H01L2224/05099 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： The present invention relates to a method for manufacturing a wafer level chip scale package structure including the following steps. After providing a glass substrate and a wafer comprising a plurality of chips, the active surface of the wafer is connected to the top surface of the glass substrate. The wafer is connected with the glass substrate through either bumps or pads thereon. After drilling the glass substrate to form a plurality of through holes, a plating process is performed to form a plurality of via plugs in the through holes. Afterwards, a singulation step is performed and a plurality of chip scale package structures is obtained.
摘要翻译：本发明涉及一种晶片级芯片级封装结构的制造方法，包括以下步骤。在提供玻璃基板和包括多个芯片的晶片之后，晶片的有效表面连接到玻璃基板的顶表面。晶片通过其上的凸块或焊盘与玻璃基板连接。在钻出玻璃基板以形成多个通孔之后，进行电镀工艺以在通孔中形成多个通孔塞。之后，进行分割步骤，并获得多个芯片级封装结构。

4. 发明授权

US07211500B2 Pre-process before cutting a wafer and method of cutting a wafer 有权
标题翻译：切割晶片前的预处理和切割晶片的方法
公开(公告)号：US07211500B2
公开(公告)日：2007-05-01
申请号：US10950909
申请日：2004-09-27
申请人： Kuo-Ming Chen , Kun-Chih Wang , Hermen Liu , Paul Chen , Kai-Kuang Ho
发明人： Kuo-Ming Chen , Kun-Chih Wang , Hermen Liu , Paul Chen , Kai-Kuang Ho
IPC分类号： H01L21/46 , H01L21/78 , H01L21/301
CPC分类号： H01L21/78
摘要： A pre-process before cutting a wafer is described. The wafer includes a plurality of scribe lines and a plurality of dies defined by the scribe lines, and a material layer covers the wafer. A pre-processing step is performed to remove the material layer on the scribe lines close to the corner regions of the dies. Removing the material layer at the corner regions before cutting the wafer is able to preserve the integrity of the corner regions of the cut dies.
摘要翻译：描述切割晶片之前的预处理。晶片包括多个划痕线和由划线限定的多个管芯，并且材料层覆盖晶片。执行预处理步骤以去除靠近模具的拐角区域的划线上的材料层。在切割晶片之前在拐角区域去除材料层能够保持切割模具的拐角区域的完整性。

5. 发明授权

US07170167B2 Method for manufacturing wafer level chip scale package structure 有权
标题翻译：制造晶圆级芯片级封装结构的方法
公开(公告)号：US07170167B2
公开(公告)日：2007-01-30
申请号：US10711536
申请日：2004-09-24
申请人： Min-Chih Hsuan , Paul Chen , Hermen Liu , Kun-Chih Wang , Kai-Kuang Ho
发明人： Min-Chih Hsuan , Paul Chen , Hermen Liu , Kun-Chih Wang , Kai-Kuang Ho
IPC分类号： H01L23/48
CPC分类号： H01L24/97 , H01L23/15 , H01L23/3114 , H01L23/3128 , H01L23/49816 , H01L24/48 , H01L24/73 , H01L24/81 , H01L24/83 , H01L2224/05001 , H01L2224/05026 , H01L2224/05568 , H01L2224/05644 , H01L2224/05647 , H01L2224/05655 , H01L2224/05664 , H01L2224/05666 , H01L2224/13111 , H01L2224/16225 , H01L2224/2929 , H01L2224/293 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/48465 , H01L2224/73265 , H01L2224/8121 , H01L2224/81815 , H01L2224/97 , H01L2924/00011 , H01L2924/00014 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/01049 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01322 , H01L2924/09701 , H01L2924/10253 , H01L2924/15311 , H01L2924/181 , H01L2924/351 , H01L2224/81 , H01L2924/00 , H01L2924/00012 , H01L2224/29075 , H01L2224/83851 , H01L2224/05099 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： The present invention relates to a method for manufacturing a wafer level chip scale package structure including the following steps. After providing a glass substrate and a wafer comprising a plurality of chips, the active surface of the wafer is connected to the top surface of the glass substrate. The wafer is connected with the glass substrate through either bumps or pads thereon. After drilling the glass substrate to form a plurality of through holes, a plating process is performed to form a plurality of via plugs in the through holes. Afterwards, a singulation step is performed and a plurality of chip scale package structures is obtained.
摘要翻译：本发明涉及一种晶片级芯片级封装结构的制造方法，包括以下步骤。在提供玻璃基板和包括多个芯片的晶片之后，晶片的有效表面连接到玻璃基板的顶表面。晶片通过其上的凸块或焊盘与玻璃基板连接。在钻出玻璃基板以形成多个通孔之后，进行电镀工艺以在通孔中形成多个通孔塞。之后，进行分割步骤，并获得多个芯片级封装结构。

6. 发明申请

US20060073676A1 Pre-process before cutting a wafer and method of cutting a wafer 有权
标题翻译：切割晶片前的预处理和切割晶片的方法
公开(公告)号：US20060073676A1
公开(公告)日：2006-04-06
申请号：US10950909
申请日：2004-09-27
申请人： Kuo-Ming Chen , Kun-Chih Wang , Hermen Liu , Paul Chen , Kai-Kuang Ho
发明人： Kuo-Ming Chen , Kun-Chih Wang , Hermen Liu , Paul Chen , Kai-Kuang Ho
IPC分类号： H01L21/78
CPC分类号： H01L21/78
摘要： A pre-process before cutting a wafer is described. The wafer comprises a plurality of scribe lines and a plurality of dies defined by the scribe lines, and a material layer covers the wafer. A pre-processing step is performed to remove the material layer on the scribe lines close to the corner regions of the dies. Removing the material layer at the corner regions before cutting the wafer is able to preserve the integrity of the corner regions of the cut dies.
摘要翻译：描述切割晶片之前的预处理。晶片包括多个划痕线和由划线限定的多个管芯，并且材料层覆盖晶片。执行预处理步骤以去除靠近模具的拐角区域的划线上的材料层。在切割晶片之前在拐角区域去除材料层能够保持切割模具的拐角区域的完整性。

7. 发明申请

US20060022195A1 SCRIBE LINE STRUCTURE 审中-公开
标题翻译：可选线结构
公开(公告)号：US20060022195A1
公开(公告)日：2006-02-02
申请号：US10710761
申请日：2004-08-01
申请人： Kun-Chih Wang
发明人： Kun-Chih Wang
IPC分类号： H01L23/58
CPC分类号： H01L22/32 , H01L2223/54426 , H01L2223/5446 , H01L2924/0002 , H01L2924/00
摘要： The present invention provides a scribe line structure, which includes a substrate, a plurality of dielectric layers of low dielectric constant materials formed on the substrate, at least a process monitor pattern made of materials of metal formed between the dielectric layers, and a dummy metal structure connected to the process monitor pattern. The dummy metal structure includes a plurality of dummy metal layers and a plurality of dummy vias. The dummy metal structure is formed on the surface of the substrate and is exposed in the region of the scribe line, thus facilitating heat dissipation and energy release from the scribe line structure.
摘要翻译：本发明提供一种划片线结构，其包括基板，形成在基板上的多个低介电常数材料的电介质层，至少由形成在电介质层之间的金属材料制成的工艺监视图案，以及虚设金属结构连接到过程监控模式。虚拟金属结构包括多个虚拟金属层和多个虚拟通孔。虚设金属结构形成在基板的表面上，并且在划线的区域中露出，从而有利于散热和从划线结构释放能量。

8. 发明授权

US06710448B2 Bonding pad structure 有权
标题翻译：粘接垫结构
公开(公告)号：US06710448B2
公开(公告)日：2004-03-23
申请号：US09880518
申请日：2001-06-12
申请人： Kun-Chih Wang
发明人： Kun-Chih Wang
IPC分类号： H01L2940
CPC分类号： H01L24/05 , H01L2224/05093 , H01L2224/05556 , H01L2924/00014 , H01L2924/01014 , H01L2924/01033 , H01L2924/01082 , H01L2924/05042 , H01L2924/10253 , H01L2924/14 , H01L2924/00
摘要： A bonding pad structure. The bonding pad structure includes independently built current conduction structure and mechanical support structure between a bonding pad layer and a substrate. The current conduction structure is constructed using a plurality of serially connected conductive metallic layers each at a different height between the bonding pad layer and the substrate. The conductive metallic layers connect with each other via a plurality of plugs. At least one of the conductive metallic layers connects electrically with a portion of the device in the substrate by a signal conduction line. The mechanical support structure is constructed using a plurality of serially connected supportive metallic layers each at a different height between the bonding pad layer and the substrate. The supportive metallic layers connect with each other via a plurality of plugs. Furthermore, the mechanical support structure connects with a non-device section of the substrate so that stresses on the bonding pads are distributed evenly through the substrate.
摘要翻译：焊盘结构。焊盘结构包括独立构建的导电结构和在焊盘层和衬底之间的机械支撑结构。电流传导结构使用在接合焊盘层和衬底之间的不同高度上的多个串联连接的导电金属层来构造。导电金属层通过多个插头彼此连接。至少一个导电金属层通过信号传导线与衬底中的器件的一部分电连接。机械支撑结构使用多个串联连接的支撑金属层来构造，每个支撑金属层在接合焊盘层和衬底之间的不同高度处。支撑金属层通过多个插头彼此连接。此外，机械支撑结构与衬底的非器件部分连接，使得焊盘上的应力均匀地分布在衬底上。

9. 发明授权

US06245380B1 Method of forming bonding pad 有权
标题翻译：形成焊盘的方法
公开(公告)号：US06245380B1
公开(公告)日：2001-06-12
申请号：US09249582
申请日：1999-02-11
申请人： Shih-Wei Sun , Wen-Yi Hsieh , Water Lur , Kun-Chih Wang
发明人： Shih-Wei Sun , Wen-Yi Hsieh , Water Lur , Kun-Chih Wang
IPC分类号： B05D512
CPC分类号： H01L24/05 , H01L21/76807 , H01L21/76847 , H01L21/76877 , H01L24/03 , H01L24/11 , H01L2224/02166 , H01L2224/0401 , H01L2224/05546 , H01L2224/05624 , H01L2224/13099 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01022 , H01L2924/01029 , H01L2924/01033 , H01L2924/0105 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/04941 , H01L2924/04953 , H01L2924/05042 , H01L2924/14 , H01L2924/00014
摘要： A method of forming bonding pad commences by forming a conformal barrier layer on a provided inter-metal dielectric layer. A first metal layer is formed on the barrier layer to partially fill the trench. A thin glue layer is formed on the first metal layer. A second metal layer is formed on the glue layer to fill the trench. The second metal layer, the glue layer, the first metal layer and the barrier layer are partially removed to expose the dielectric layer. A bonding pad structure is thus formed in the trench. The bonding pad structure comprises a first metal pad and a second metal pad.
摘要翻译：通过在所提供的金属间介电层上形成保形阻挡层，开始形成焊盘的方法。在阻挡层上形成第一金属层以部分地填充沟槽。在第一金属层上形成薄胶层。在胶层上形成第二金属层以填充沟槽。部分去除第二金属层，胶层，第一金属层和阻挡层，以露出介质层。因此在沟槽中形成接合焊盘结构。焊盘结构包括第一金属焊盘和第二金属焊盘。

10. 发明授权

US6046097A Deposition method with improved step coverage 有权
标题翻译：沉积方法具有改进的台阶覆盖
公开(公告)号：US6046097A
公开(公告)日：2000-04-04
申请号：US274599
申请日：1999-03-23
申请人： Kevin Hsieh , Kun-Chih Wang , Wen-Yi Hsieh
发明人： Kevin Hsieh , Kun-Chih Wang , Wen-Yi Hsieh
IPC分类号： H01L21/768 , H01L21/28
CPC分类号： H01L21/76843
摘要： A deposition method for improving the step coverage of contact holes is disclosed. The method includes initially placing a semiconductor substrate on a chuck of a chamber, wherein the substrate has some contact holes. The chuck is firstly adjusted and conductive material is firstly deposited onto the substrate, wherein the direction of the first deposition is about vertical to the surface of the substrate, and therefore the bottom of the contact holes is then substantially deposited with the conductive material. Next, the chuck is secondly adjusted so that it has a tilt angle between the direction of the second deposition and rotation axis of the chuck. Finally, the chuck is continuously rotated and the conductive material is secondly deposited onto the substrate, and therefore the sidewall of the contact holes is then substantially deposited with the conductive material.
摘要翻译：公开了一种用于改善接触孔的台阶覆盖的沉积方法。该方法包括最初将半导体衬底放置在室的卡盘上，其中衬底具有一些接触孔。首先调整卡盘，并且首先将导电材料沉积到基底上，其中第一沉积的方向大约垂直于基底的表面，因此接触孔的底部然后基本上沉积有导电材料。接下来，卡盘被二次调节，使得其在第二沉积的方向和卡盘的旋转轴线之间具有倾斜角。最后，卡盘连续旋转，导电材料第二次沉积在基片上，因此接触孔的侧壁然后基本上沉积有导电材料。

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