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1. 发明申请

US20060154817A1 Substrate for exhaust-gas purifying filter catalyst 失效
标题翻译：废气净化过滤器催化剂底物
公开(公告)号：US20060154817A1
公开(公告)日：2006-07-13
申请号：US10545814
申请日：2004-02-13
申请人： Kumiko Nomura , Satoko Inuduka
发明人： Kumiko Nomura , Satoko Inuduka
IPC分类号： B01J21/04
CPC分类号： B01D46/2429 , B01D46/2425 , B01D53/9422 , B01D2255/202 , B01D2255/204 , B01D2255/915 , B01D2275/30 , B01J23/42 , B01J23/58 , B01J23/63 , B01J35/002 , B01J35/04 , B01J35/1052 , B01J37/0242 , C04B38/0006 , C04B2111/00612 , C04B2111/00793 , C04B2111/0081 , F01N3/0222 , F01N3/035 , F01N3/0821 , F01N3/0842 , F01N2250/02 , F01N2330/06 , C04B35/00 , C04B38/0051
摘要： In the distribution of surface vacancies which open on the surface of the cellular walls of pores, more than 8% of total opening area of all surface vacancies that the pores are open on the surface of the cellular walls is occupied by total opening area of surface vacancies having maximum diameter of from 10 to 50 μm measured by a direct observation method and, in the distribution of inner pores, more than 20% of total cross-sectional area of all pores is occupied by total cross-sectional area of pores having cross-sectional area equivalent to that of a circle having diameter more than 300 μm measured by cross-sectional observation using CT scan. Even when a large amount of PMs are emitted densely at a short time, since they are dispersed and collected by each pore, PM deposition is controlled and the increase of the pressure loss is suppressed, as well as collecting efficiency is improved.
摘要翻译：在孔的细胞壁表面开放的表面空位的分布中，在孔壁表面上孔开放的所有表面空位的总开口面积的8％以上占据了表面的总开口面积通过直接观察方法测量的最大直径为10至50μm的空位，并且在内孔的分布中，所有孔的总横截面面积的20％以上占全部横截面积的横截面积通过使用CT扫描的横截面观察来测量直径大于300μm的圆的面积面积。即使大量的PM在短时间内密集地发射，由于它们被每个孔分散和收集，所以PM沉积被控制并且压力损失的增加被抑制，并且提高了收集效率。

2. 发明授权

US07517830B2 Substrate for exhaust-gas purifying filter catalyst 失效
标题翻译：废气净化过滤器催化剂底物
公开(公告)号：US07517830B2
公开(公告)日：2009-04-14
申请号：US10545814
申请日：2004-02-13
申请人： Kumiko Nomura , Satoko Inuduka
发明人： Kumiko Nomura , Satoko Inuduka
IPC分类号： B01J23/02 , B01J23/10 , B01J23/38 , B01J32/00 , B01J35/04
CPC分类号： B01D46/2429 , B01D46/2425 , B01D53/9422 , B01D2255/202 , B01D2255/204 , B01D2255/915 , B01D2275/30 , B01J23/42 , B01J23/58 , B01J23/63 , B01J35/002 , B01J35/04 , B01J35/1052 , B01J37/0242 , C04B38/0006 , C04B2111/00612 , C04B2111/00793 , C04B2111/0081 , F01N3/0222 , F01N3/035 , F01N3/0821 , F01N3/0842 , F01N2250/02 , F01N2330/06 , C04B35/00 , C04B38/0051
摘要： In the distribution of surface vacancies which open on the surface of the cellular walls of pores, more than 8% of total opening area of all surface vacancies that the pores are open on the surface of the cellular walls is occupied by total opening area of surface vacancies having maximum diameter of from 10 to 50 μm, in the distribution of inner pores, more than 20% of total cross-sectional area of all pores is occupied by total cross-sectional area of pores having cross-sectional area equivalent to that of a circle having diameter more than 300 μm.
摘要翻译：在孔的细胞壁表面开放的表面空位的分布中，在孔壁表面上孔开放的所有表面空位的总开口面积的8％以上占据了表面的总开口面积最大直径为10至50um的空隙，在内孔分布中，所有孔的总横截面面积的20％以上的横截面面积占总截面面积的横截面面积相当于直径大于300μm的圆。

3. 发明申请

US20090217222A1 SEMICONDUCTOR INTEGRATED CIRCUIT 审中-公开
标题翻译：半导体集成电路
公开(公告)号：US20090217222A1
公开(公告)日：2009-08-27
申请号：US12211842
申请日：2008-09-17
申请人： Shinichi Yasuda , Kumiko Nomura , Keiko Abe
发明人： Shinichi Yasuda , Kumiko Nomura , Keiko Abe
IPC分类号： G06F17/50
CPC分类号： G06F11/006 , G06F11/2242
摘要： A semiconductor integrated circuit includes: a plurality of processor elements each including a test circuit which tests whether there is a failure in the processor element and outputs a result of the test; a plurality of switch boxes provided so as to be respectively associated with processor elements, each of the switch boxes configured to have a table to store information of another processor element and transmit information of a corresponding processor element to the other processor element based on information stored in the table; a plurality of identification circuits provided so as to be respectively associated with processor elements, each of the identification circuits configured to identify a defective processor element on the basis of the result of the test and output location information of the defective processor element; and a transmission circuit configured to transmit the location information of the defective processor element output from the identification circuit to the switch boxes.
摘要翻译：半导体集成电路包括：多个处理器元件，每个处理器元件包括测试电路，该测试电路测试处理器元件中是否存在故障并输出测试结果; 设置为分别与处理器元件相关联的多个开关盒，每个开关盒被配置为具有用于存储另一个处理器元件的信息的表格，并且基于存储的信息将相应的处理器元件的信息发送到另一个处理器元件在桌子上设置为分别与处理器元件相关联的多个识别电路，每个识别电路被配置为基于测试的结果和缺陷处理器元件的输出位置信息来识别有缺陷的处理器元件; 以及发送电路，被配置为将从识别电路输出的缺陷处理器元件的位置信息发送到开关盒。

4. 发明授权

US08680887B2 Nonvolatile configuration memory 失效
标题翻译：非易失配置存储器
公开(公告)号：US08680887B2
公开(公告)日：2014-03-25
申请号：US13419205
申请日：2012-03-13
申请人： Keiko Abe , Shinichi Yasuda , Kumiko Nomura , Shinobu Fujita
发明人： Keiko Abe , Shinichi Yasuda , Kumiko Nomura , Shinobu Fujita
IPC分类号： H03K19/177 , G11C11/34 , G11C16/04 , G11C11/00
CPC分类号： H03K19/1776 , G11C11/412 , G11C14/0063
摘要： According to one embodiment, a memory includes a first P-channel FET having a gate connected to a second output node, a source applied to a first potential, and a drain connected to the first output node, a second P-channel FET having a gate connected to a first output node, a source applied to the first potential, and a drain connected to the second output node, a first N-channel FET having a control gate connected to a first word line, a source applied to a second potential lower than the first potential, a drain connected to the first output node, and a threshold changed by data in a storage layer, and a second N-channel FET having a control gate connected to a second word line, a source applied to the second potential, a drain connected to the second output node, and a threshold changed by data in a storage layer.
摘要翻译：根据一个实施例，存储器包括：第一P沟道FET，其具有连接到第二输出节点的栅极，施加到第一电位的源极和连接到第一输出节点的漏极;第二P沟道FET，其具有连接到第一输出节点的源极，施加到第一电位的源极和连接到第二输出节点的漏极，具有连接到第一字线的控制栅极的第一N沟道FET，施加到第二电位的源极低于第一电位的漏极，连接到第一输出节点的漏极和由存储层中的数据改变的阈值，以及具有连接到第二字线的控制栅极的第二N沟道FET，施加到第二电压的源极电位，连接到第二输出节点的漏极以及由存储层中的数据改变的阈值。

5. 发明授权

US08437187B2 Semiconductor integrated circuit including memory cells having non-volatile memories and switching elements 有权
标题翻译：包括具有非易失性存储器和开关元件的存储单元的半导体集成电路
公开(公告)号：US08437187B2
公开(公告)日：2013-05-07
申请号：US13232550
申请日：2011-09-14
申请人： Shinichi Yasuda , Masato Oda , Kumiko Nomura , Keiko Abe , Shinobu Fujita
发明人： Shinichi Yasuda , Masato Oda , Kumiko Nomura , Keiko Abe , Shinobu Fujita
IPC分类号： G11C16/04 , G11C7/10
CPC分类号： H03K19/17728 , G11C13/0002 , G11C16/0466 , H03K19/17768
摘要： In one embodiment, a semiconductor integrated circuit has memory cells. Each of the memory cells has non-volatile memories and switching elements. The non-volatile memories and switching elements are connected in series between a first power source and a second power source. Output wirings of at least two of the memory cells are connected to each other. Input wirings are connected with control gates of the switching elements included in each of the at least two memory cells. A plurality of the switching elements included in one of the at least two of the memory cells is turned off, when an input signal or an inverted signal is inputted. Further, another plurality of the switching elements included in another one of the at least two of memory cells other than the one of the memory cells is turned on, when the input signal or the inverted signal is inputted.
摘要翻译：在一个实施例中，半导体集成电路具有存储单元。每个存储单元具有非易失性存储器和开关元件。非易失性存储器和开关元件串联连接在第一电源和第二电源之间。至少两个存储单元的输出布线彼此连接。输入布线与包括在至少两个存储单元中的每一个中的开关元件的控制栅极连接。当输入信号或反相信号被输入时，包括在至少两个存储单元之一中的多个开关元件被断开。此外，当输入信号或反相信号被输入时，包括在存储单元之外的至少两个存储单元中的另一个存储单元中的另外多个开关元件导通。

6. 发明申请

US20120230105A1 Semiconductor Integrated Circuit 有权
标题翻译：半导体集成电路
公开(公告)号：US20120230105A1
公开(公告)日：2012-09-13
申请号：US13232550
申请日：2011-09-14
申请人： Shinichi YASUDA , Masato Oda , Kumiko Nomura , Keiko Abe , Shinobu Fujita
发明人： Shinichi YASUDA , Masato Oda , Kumiko Nomura , Keiko Abe , Shinobu Fujita
IPC分类号： G11C16/04 , G11C5/06
CPC分类号： H03K19/17728 , G11C13/0002 , G11C16/0466 , H03K19/17768
摘要： In one embodiment, a semiconductor integrated circuit has memory cells. Each of the memory cells has non-volatile memories and switching elements. The non-volatile memories and switching elements are connected in series between a first power source and a second power source. Output wirings of at least two of the memory cells are connected to each other. Input wirings are connected with control gates of the switching elements included in each of the at least two memory cells. A plurality of the switching elements included in one of the at least two of the memory cells is turned off, when an input signal or an inverted signal is inputted. Further, another plurality of the switching elements included in another one of the at least two of memory cells other than the one of the memory cells is turned on, when the input signal or the inverted signal is inputted.
摘要翻译：在一个实施例中，半导体集成电路具有存储单元。每个存储单元具有非易失性存储器和开关元件。非易失性存储器和开关元件串联连接在第一电源和第二电源之间。至少两个存储单元的输出布线彼此连接。输入布线与包括在至少两个存储单元中的每一个中的开关元件的控制栅极连接。当输入信号或反相信号被输入时，包括在至少两个存储单元之一中的多个开关元件被断开。此外，当输入信号或反相信号被输入时，包括在存储单元之外的至少两个存储单元中的另一个存储单元中的另外多个开关元件导通。

7. 发明授权

US11901568B2 Electrocatalyst 有权
公开(公告)号：US11901568B2
公开(公告)日：2024-02-13
申请号：US17653400
申请日：2022-03-03
申请人： Ryo Shimizu , Kumiko Nomura , Tomohiro Takeshita , Shu Miyasaka , Kenji Yamamoto
发明人： Ryo Shimizu , Kumiko Nomura , Tomohiro Takeshita , Shu Miyasaka , Kenji Yamamoto
IPC分类号： H01M4/00 , H01M4/92 , H01M4/88 , C22C5/04
CPC分类号： H01M4/926 , H01M4/8842 , C22C5/04
摘要： To provide an electrocatalyst for fuel cells, which is configured to ensure both the initial performance and durability of fuel cells. An electrocatalyst for fuel cells, wherein the electrocatalyst comprises a carbon support including a mesopore and a catalyst alloy supported on the carbon support, and the catalyst alloy is a catalyst alloy of platinum and a transition metal; wherein the mesopore includes at least one throat; wherein an average effective diameter of the at least one throat is 1.8 nm or more and less than 3.2 nm; and wherein a transition metal ratio of the catalyst alloy supported on a deeper-side region than the at least one throat, is lower than the transition metal ratio of the catalyst alloy supported on a nearer-side region than the at least one throat.

8. 发明授权

US08578318B2 Method for implementing circuit design for integrated circuit and computer readable medium 失效
标题翻译：集成电路和计算机可读介质电路设计实现方法
公开(公告)号：US08578318B2
公开(公告)日：2013-11-05
申请号：US13561483
申请日：2012-07-30
申请人： Kumiko Nomura , Shinichi Yasuda , Shinobu Fujita , Keiko Abe , Tetsufumi Tanamoto , Kazutaka Ikegami , Masato Oda
发明人： Kumiko Nomura , Shinichi Yasuda , Shinobu Fujita , Keiko Abe , Tetsufumi Tanamoto , Kazutaka Ikegami , Masato Oda
IPC分类号： G06F17/50
CPC分类号： G06F17/5077 , G06F17/5031 , G06F17/5054 , G06F17/5081
摘要： In one embodiment, a method for implementing a circuit design for an integrated circuit includes: (a) obtaining a first wiring to satisfy a given operating frequency; (b) calculating a maximum bypass wiring length based on the given operating frequency and a critical path of the first wiring; (c) obtaining a second wiring by bypassing the first wiring using wires other than wires of the first wiring in a first wiring group, wherein wiring of the integrated circuit is categorized into a plurality of wiring groups, and the first wiring is included in the first wiring group of the categorized wiring groups; and (d) replacing the first wiring with the second wiring, if a difference between the second wiring and the first wiring is not larger than the maximum bypass wiring length, and not replacing the first wiring if said difference is larger than the maximum bypass wiring length.
摘要翻译：在一个实施例中，一种用于实现集成电路的电路设计的方法包括：（a）获得第一布线以满足给定的工作频率; （b）基于给定的工作频率和第一布线的关键路径计算最大旁路布线长度; （c）通过在第一布线组中使用不同于第一布线的布线的旁路第一布线来获得第二布线，其中集成电路的布线被分类为多个布线组，并且第一布线包括在第一布线中分类布线组的第一接线组; 以及（d）如果所述第二布线和所述第一布线之间的差不大于所述最大旁路布线长度，则用所述第二布线代替所述第一布线，并且如果所述差大于所述最大旁路布线，则不更换所述第一布线长度。

9. 发明申请

US20080243978A1 RANDOM NUMBER GENERATOR 审中-公开
标题翻译：随机数发电机
公开(公告)号：US20080243978A1
公开(公告)日：2008-10-02
申请号：US12050079
申请日：2008-03-17
申请人： Shinichi Yasuda , Keiko Abe , Tetsufumi Tanamoto , Kumiko Nomura
发明人： Shinichi Yasuda , Keiko Abe , Tetsufumi Tanamoto , Kumiko Nomura
IPC分类号： G06F7/58
CPC分类号： G06F7/588
摘要： A random number generator includes an amplifier to amplify a difference between a noise signal and a reference signal to generate an amplified signal, a plurality of binarization circuits configured to binarize the amplified signal by using different inherent threshold values to obtain a plurality of binarized signals, and an exclusive OR circuit to perform an exclusive OR operation on the a plurality of binarized signals to generate random number sequence.
摘要翻译：随机数发生器包括：放大器，用于放大噪声信号和参考信号之间的差以产生放大信号;多个二值化电路，被配置为通过使用不同的固有阈值二值化放大的信号，以获得多个二值化信号; 以及异或电路，对多个二值化信号进行异或运算，生成随机数序列。

10. 发明授权

US08724403B2 Cache system and information-processing device 有权
标题翻译：缓存系统和信息处理设备
公开(公告)号：US08724403B2
公开(公告)日：2014-05-13
申请号：US13729382
申请日：2012-12-28
申请人： Kumiko Nomura , Shinobu Fujita , Keiko Abe , Kazutaka Ikegami , Hiroki Noguchi
发明人： Kumiko Nomura , Shinobu Fujita , Keiko Abe , Kazutaka Ikegami , Hiroki Noguchi
IPC分类号： G11C7/06
CPC分类号： G06F1/3206 , G06F1/3225 , G06F1/3275 , Y02D10/13 , Y02D10/14
摘要： According to one embodiment, a cache system includes a tag memory includes a volatile memory device, the tag memory includes ways and storing a tag for each line, a data memory includes a nonvolatile memory device including sense amplifiers for reading data, the data memory includes ways and storing data for each line, a comparison circuit configured to compare a tag included in an address supplied from an external with a tag read from the tag memory, and a controller configured to turn off a power of a sense amplifier for a way which is not accessed based on a comparison result of the comparison circuit.
摘要翻译：根据一个实施例，缓存系统包括标签存储器，其包括易失性存储器设备，标签存储器包括每条线路的方式和存储标签，数据存储器包括包括用于读取数据的读出放大器的非易失性存储器件，数据存储器包括方式和存储每行的数据，比较电路，被配置为将从外部提供的地址中包含的标签与从标签存储器读取的标签进行比较，以及控制器，被配置为关闭读出放大器的功率，基于比较电路的比较结果不被访问。

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