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    • 3. 发明申请
    • SEMICONDUCTOR INTEGRATED CIRCUIT
    • 半导体集成电路
    • US20090217222A1
    • 2009-08-27
    • US12211842
    • 2008-09-17
    • Shinichi YasudaKumiko NomuraKeiko Abe
    • Shinichi YasudaKumiko NomuraKeiko Abe
    • G06F17/50
    • G06F11/006G06F11/2242
    • A semiconductor integrated circuit includes: a plurality of processor elements each including a test circuit which tests whether there is a failure in the processor element and outputs a result of the test; a plurality of switch boxes provided so as to be respectively associated with processor elements, each of the switch boxes configured to have a table to store information of another processor element and transmit information of a corresponding processor element to the other processor element based on information stored in the table; a plurality of identification circuits provided so as to be respectively associated with processor elements, each of the identification circuits configured to identify a defective processor element on the basis of the result of the test and output location information of the defective processor element; and a transmission circuit configured to transmit the location information of the defective processor element output from the identification circuit to the switch boxes.
    • 半导体集成电路包括:多个处理器元件,每个处理器元件包括测试电路,该测试电路测试处理器元件中是否存在故障并输出测试结果; 设置为分别与处理器元件相关联的多个开关盒,每个开关盒被配置为具有用于存储另一个处理器元件的信息的表格,并且基于存储的信息将相应的处理器元件的信息发送到另一个处理器元件 在桌子上 设置为分别与处理器元件相关联的多个识别电路,每个识别电路被配置为基于测试的结果和缺陷处理器元件的输出位置信息来识别有缺陷的处理器元件; 以及发送电路,被配置为将从识别电路输出的缺陷处理器元件的位置信息发送到开关盒。
    • 4. 发明授权
    • Nonvolatile configuration memory
    • 非易失配置存储器
    • US08680887B2
    • 2014-03-25
    • US13419205
    • 2012-03-13
    • Keiko AbeShinichi YasudaKumiko NomuraShinobu Fujita
    • Keiko AbeShinichi YasudaKumiko NomuraShinobu Fujita
    • H03K19/177G11C11/34G11C16/04G11C11/00
    • H03K19/1776G11C11/412G11C14/0063
    • According to one embodiment, a memory includes a first P-channel FET having a gate connected to a second output node, a source applied to a first potential, and a drain connected to the first output node, a second P-channel FET having a gate connected to a first output node, a source applied to the first potential, and a drain connected to the second output node, a first N-channel FET having a control gate connected to a first word line, a source applied to a second potential lower than the first potential, a drain connected to the first output node, and a threshold changed by data in a storage layer, and a second N-channel FET having a control gate connected to a second word line, a source applied to the second potential, a drain connected to the second output node, and a threshold changed by data in a storage layer.
    • 根据一个实施例,存储器包括:第一P沟道FET,其具有连接到第二输出节点的栅极,施加到第一电位的源极和连接到第一输出节点的漏极;第二P沟道FET,其具有 连接到第一输出节点的源极,施加到第一电位的源极和连接到第二输出节点的漏极,具有连接到第一字线的控制栅极的第一N沟道FET,施加到第二电位的源极 低于第一电位的漏极,连接到第一输出节点的漏极和由存储层中的数据改变的阈值,以及具有连接到第二字线的控制栅极的第二N沟道FET,施加到第二电压的源极 电位,连接到第二输出节点的漏极以及由存储层中的数据改变的阈值。
    • 6. 发明申请
    • Semiconductor Integrated Circuit
    • 半导体集成电路
    • US20120230105A1
    • 2012-09-13
    • US13232550
    • 2011-09-14
    • Shinichi YASUDAMasato OdaKumiko NomuraKeiko AbeShinobu Fujita
    • Shinichi YASUDAMasato OdaKumiko NomuraKeiko AbeShinobu Fujita
    • G11C16/04G11C5/06
    • H03K19/17728G11C13/0002G11C16/0466H03K19/17768
    • In one embodiment, a semiconductor integrated circuit has memory cells. Each of the memory cells has non-volatile memories and switching elements. The non-volatile memories and switching elements are connected in series between a first power source and a second power source. Output wirings of at least two of the memory cells are connected to each other. Input wirings are connected with control gates of the switching elements included in each of the at least two memory cells. A plurality of the switching elements included in one of the at least two of the memory cells is turned off, when an input signal or an inverted signal is inputted. Further, another plurality of the switching elements included in another one of the at least two of memory cells other than the one of the memory cells is turned on, when the input signal or the inverted signal is inputted.
    • 在一个实施例中,半导体集成电路具有存储单元。 每个存储单元具有非易失性存储器和开关元件。 非易失性存储器和开关元件串联连接在第一电源和第二电源之间。 至少两个存储单元的输出布线彼此连接。 输入布线与包括在至少两个存储单元中的每一个中的开关元件的控制栅极连接。 当输入信号或反相信号被输入时,包括在至少两个存储单元之一中的多个开关元件被断开。 此外,当输入信号或反相信号被输入时,包括在存储单元之外的至少两个存储单元中的另一个存储单元中的另外多个开关元件导通。