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1. 发明授权

US4843023A Process for forming lightly-doped-drain (LDD) without extra masking steps 失效
标题翻译：用于形成轻掺杂漏极（LDD）的工艺，无需额外的掩模步骤
公开(公告)号：US4843023A
公开(公告)日：1989-06-27
申请号：US65617
申请日：1987-06-30
申请人： Kuang Y. Chiu , Fu-Chieh Hsu
发明人： Kuang Y. Chiu , Fu-Chieh Hsu
IPC分类号： H01L21/033 , H01L21/336 , H01L21/8238 , H01L29/78
CPC分类号： H01L29/6659 , H01L21/0337 , H01L21/823864 , H01L29/6656 , H01L29/78
摘要： A new lightly doped drain (LDD) process which does not required extra masking steps as compared to the conventional CMOS process is presented. By employing a new two layer side wall spacer technology, the LDD ion implantation for n-channel and p-channel devices can be carried out by sharing the n.sup.+ or p.sup.+ source and drain ion implantation mask. This approach provides maximum flexibility in designing optimum n.sup.- and p.sup.- channel LDD MOSFETs without using any additional mask steps other than the conventional CMOS mask levels. This process is also compatible with self-aligned silicide process.
摘要翻译：提出了与常规CMOS工艺相比不需要额外掩模步骤的新的轻掺杂漏极（LDD）工艺。通过采用新的双层侧壁间隔技术，n沟道和p沟道器件的LDD离子注入可以通过共享n +或p +源极和漏极离子注入掩模进行。这种方法在设计最佳的n沟道和p沟道LDD MOSFET时提供了最大的灵活性，而不需要采用常规CMOS掩模级别以外的任何附加掩模步骤。该工艺也与自对准硅化物工艺兼容。

2. 发明授权

US4398992A Defect free zero oxide encroachment process for semiconductor fabrication 失效
标题翻译：用于半导体制造的无缺陷的零氧化物侵蚀过程
公开(公告)号：US4398992A
公开(公告)日：1983-08-16
申请号：US380195
申请日：1982-05-20
申请人： Robert C. Y. Fang , Kuang Y. Chiu
发明人： Robert C. Y. Fang , Kuang Y. Chiu
IPC分类号： H01L21/76 , H01L21/316 , H01L21/32 , H01L21/762 , H01L21/306 , B44C1/22 , C03C15/00 , C03C25/06
CPC分类号： H01L21/76205 , H01L21/32
摘要： A method for local oxideation of a semiconductor using only conventional large scale integration (LSI) fabrication techniques is provided which results in an oxide layer without the formation of the so-called "bird's beak" structure and no process or structure induced defects. On a semiconductor substrate a mold for oxide is made by forming on the substrate, a trench with sidewalls extending upward to a localized mesa region of the substrate. The sidewalls of the mesa, the localized plateau and a distance out from the sidewalls of the mesa to a desired distance out from the sidewalls are covered by a masking layer capable of preventing oxideation of the underlying substrate. The unmasked portion of the mold is oxidized to produce a localized oxide layer which is substantially free of any "bird's beak" structure.
摘要翻译：提供了仅使用常规大规模集成（LSI）制造技术来半导体的局部氧化的方法，其导致氧化物层，而不形成所谓的“鸟喙”结构，并且没有工艺或结构引起的缺陷。在半导体衬底上，通过在衬底上形成具有向上延伸到衬底的局部台面区域的侧壁的沟槽来制造用于氧化物的模具。台面的侧壁，局部平台以及从台面的侧壁离开到侧壁的期望距离之间的距离由能够防止下面的基底的氧化作用的掩模层覆盖。模具的未掩模部分被氧化以产生基本上没有任何“鸟喙”结构的局部氧化物层。

3. 发明授权

US5401998A Trench isolation using doped sidewalls 失效
标题翻译：使用掺杂侧壁进行沟槽隔离
公开(公告)号：US5401998A
公开(公告)日：1995-03-28
申请号：US296611
申请日：1994-08-26
申请人： Kuang Y. Chiu , Dan W. Peters
发明人： Kuang Y. Chiu , Dan W. Peters
IPC分类号： H01L21/76 , H01L21/306 , H01L21/762 , H01L27/088 , H01L27/04
CPC分类号： H01L21/30608 , H01L21/76224 , H01L21/76232 , H01L21/76237 , H01L27/088
摘要： A P-type substrate is immersed in a solution of potassium hydroxide (KOH) which etches exposed portions of the substrate to form trenches with sidewalls at an angle of 54.7 degrees with respect to the top surface of the substrate. A vertical boron implant is then conducted which implants boron ions into the angled sidewalls of the trenches. A layer of oxide is then deposited over the substrate surface to fill the trenches approximately flush with the surface of the substrate. NMOS transistors may then be formed in the islands surrounded by the trenches so as to be isolated from other NMOS devices. The boron doping of the sidewalls prevents the inversion of the sidewalls due to any charged contaminants in the deposited oxide. This avoids parasitic leakage currents between the N-type source and drain regions of the NMOS transistors which abut the sidewalls of the trenches.
摘要翻译：将P型衬底浸入氢氧化钾（KOH）的溶液中，该溶液蚀刻衬底的暴露部分，形成具有相对于衬底顶表面54.7度的侧壁的沟槽。然后进行垂直硼注入，其将硼离子注入到沟槽的倾斜侧壁中。然后将一层氧化物沉积在衬底表面上以填充大致与衬底的表面齐平的沟槽。然后可以在由沟槽围绕的岛中形成NMOS晶体管，以便与其他NMOS器件隔离。侧壁的硼掺杂防止由于沉积的氧化物中的任何带电污染物导致的侧壁反转。这避免了邻接沟槽侧壁的NMOS晶体管的N型源区和漏区之间的寄生漏电流。

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