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1. 发明授权

US07376691B2 Arithmetic and logic unit using half adder 失效
标题翻译：使用半加法器的算术和逻辑单元
公开(公告)号：US07376691B2
公开(公告)日：2008-05-20
申请号：US10849665
申请日：2004-05-20
申请人： Ku Rak Jung , Jun Hee Kang , Alex F. Kirichenko , Saad Sarwana
发明人： Ku Rak Jung , Jun Hee Kang , Alex F. Kirichenko , Saad Sarwana
IPC分类号： G06F7/50
CPC分类号： G06F7/57
摘要： The present invention discloses an ALU (Arithmetic Logic Unit) that can be operated as an OR gate, an AND gate, an adder gate and an exclusive OR gate using a half adder that uses a superconductor rapid single flux quantum logic device. The ALU using a half adder includes a half adder using a superconductor rapid single flux quantum logic device as a logic circuit, and a switching unit that has input ports respectively connected to a sum output port and a carry output port of the half adder and is operated as an OR gate, an AND gate, an adder gate and an exclusive OR gate using output signals of the half adder. The switching unit includes a first switch having an input port connected to the sum output port of the half adder, a second switch having an input port connected to the carry output port of the half adder and an output port connected to an output port of the first switch, and a third switch having an input port connected to the carry output port of the half adder.
摘要翻译：本发明公开了一种ALU（算术逻辑单元），其可以使用使用超导体快速单通量量子逻辑器件的半加法器作为或门，与门，加法器门和异或门来操作。使用半加法器的ALU包括使用超导体快速单通量量子逻辑器件作为逻辑电路的半加法器，以及具有分别连接到半加法器的和输出端口和进位输出端口的输入端口的开关单元，并且是作为或门，与门，加法器门和使用半加法器的输出信号的异或门运算。开关单元包括具有连接到半加法器的和输出端口的输入端口的第一开关，具有连接到半加法器的进位输出端口的输入端口的第二开关和连接到半加法器的输出端口的输出端口第一开关和具有连接到半加法器的进位输出端口的输入端口的第三开关。

2. 发明申请

US20110167241A1 SUPERCONDUCTING CIRCUIT FOR HIGH-SPEED LOOKUP TABLE 审中-公开
标题翻译：用于高速查看表的超级电路
公开(公告)号：US20110167241A1
公开(公告)日：2011-07-07
申请号：US13043272
申请日：2011-03-08
申请人： Alex F. Kirichenko , Timur V. Filippov , Deepnarayan Gupta
发明人： Alex F. Kirichenko , Timur V. Filippov , Deepnarayan Gupta
IPC分类号： G06F15/00 , G06F9/30
CPC分类号： G11C8/10 , Y10S505/831 , Y10S505/837
摘要： A high-speed lookup table is designed using Rapid Single Flux Quantum (RSFQ) logic elements and fabricated using superconducting integrated circuits. The lookup table is composed of an address decoder and a programmable read-only memory array (PROM). The memory array has rapid parallel pipelined readout and slower serial reprogramming of memory contents. The memory cells are constructed using standard non-destructive reset-set flip-flops (RSN cells) and data flip-flops (DFF cells). An n-bit address decoder is implemented in the same technology and closely integrated with the memory array to achieve high-speed operation as a lookup table. The circuit architecture is scalable to large two-dimensional data arrays.
摘要翻译：使用快速单通量量子（RSFQ）逻辑元件设计高速查找表，并使用超导集成电路制造。查找表由地址解码器和可编程只读存储器阵列（PROM）组成。存储器阵列具有快速的并行流水线读出和较慢的存储器内容的串行重新编程。使用标准的非破坏性复位触发器（RSN单元）和数据触发器（DFF单元）构建存储单元。 n位地址解码器以相同的技术实现并与存储器阵列紧密集成，以实现作为查找表的高速操作。电路架构可扩展到大型二维数据阵列。

3. 发明授权

US07443719B2 Superconducting circuit for high-speed lookup table 失效
标题翻译：超导电路用于高速查找表
公开(公告)号：US07443719B2
公开(公告)日：2008-10-28
申请号：US11360749
申请日：2006-02-23
申请人： Alex F. Kirichenko , Timur V. Filippov , Deepnarayan Gupta
发明人： Alex F. Kirichenko , Timur V. Filippov , Deepnarayan Gupta
IPC分类号： G11C11/44
CPC分类号： G11C8/10 , Y10S505/831 , Y10S505/837
摘要： A high-speed lookup table is designed using Rapid Single Flux Quantum (RSFQ) logic elements and fabricated using superconducting integrated circuits. The lookup table is composed of an address decoder and a programmable read-only memory array (PROM). The memory array has rapid parallel pipelined readout and slower serial reprogramming of memory contents. The memory cells are constructed using standard non-destructive reset-set flip-flops (RSN cells) and data flip-flops (DFF cells). An n-bit address decoder is implemented in the same technology and closely integrated with the memory array to achieve high-speed operation as a lookup table. The circuit architecture is scalable to large two-dimensional data arrays.
摘要翻译：使用快速单通量量子（RSFQ）逻辑元件设计高速查找表，并使用超导集成电路制造。查找表由地址解码器和可编程只读存储器阵列（PROM）组成。存储器阵列具有快速的并行流水线读出和较慢的存储器内容的串行重新编程。使用标准的非破坏性复位触发器（RSN单元）和数据触发器（DFF单元）构建存储单元。 n位地址解码器以相同的技术实现并与存储器阵列紧密集成，以实现作为查找表的高速操作。电路架构可扩展到大型二维数据阵列。

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