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    • 2. 发明授权
    • Cache memory system having data and tag arrays and multi-purpose buffer
assembly with multiple line buffers
    • 具有数据和标签数组的高速缓冲存储器系统以及具有多个行缓冲器的多用途缓冲器组件
    • US5680572A
    • 1997-10-21
    • US680109
    • 1996-07-15
    • Haitham AkkaryJeffrey M. AbramsonAndrew F. GlewGlenn J. HintonKris G. KonigsfeldPaul D. MadlandMandar S. JoshiBrent E. Lince
    • Haitham AkkaryJeffrey M. AbramsonAndrew F. GlewGlenn J. HintonKris G. KonigsfeldPaul D. MadlandMandar S. JoshiBrent E. Lince
    • G06F12/08
    • G06F12/0859
    • A data cache and a plurality of companion fill buffers having corresponding tag matching circuitry are provided to a computer system. Each fill buffer independently stores and tracks a replacement cache line being filled with data returning from main memory in response to a cache miss. When the cache fill is completed, the replacement cache line is output for the cache tag and data arrays of the data cache if the memory locations are cacheable and the cache line has not been snoop hit while the cache fill was in progress. Additionally, the fill buffers are organized and provided with sufficient address and data ports as well as selectors to allow the fill buffers to respond to subsequent processor loads and stores, and external snoops that hit their cache lines while the cache fills are in progress. As a result, the cache tag and data arrays of the data cache can continue to serve subsequent processor loads and stores, and external snoops, while one or more cache fills are in progress, without ever having to stall the processor.
    • 具有对应的标签匹配电路的数据高速缓存和多个伴随填充缓冲器被提供给计算机系统。 每个填充缓冲器独立地存储和跟踪填充有响应于高速缓存未命中从主存储器返回的数据的替换高速缓存行。 当缓存填充完成时,如果内存位置是可高速缓存的,并且缓存填充正在进行时,缓存线尚未被窥探,则会为高速缓存标签和数据高速缓存的数据阵列输出替换高速缓存行。 此外,填充缓冲区被组织并提供有足够的地址和数据端口以及选择器,以允许填充缓冲区响应后续处理器负载和存储,以及在高速缓存填充正在进行时触发其缓存行的外部监听。 因此,数据高速缓存的高速缓存标签和数据阵列可以在一个或多个缓存填充正在进行的同时继续提供后续的处理器加载和存储以及外部监听,而无需停止处理器。