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1. 发明授权

US06640287B2 Scalable multiprocessor system and cache coherence method incorporating invalid-to-dirty requests 失效
公开(公告)号：US06640287B2
公开(公告)日：2003-10-28
申请号：US10042009
申请日：2002-01-07
申请人： Kourosh Gharachorloo , Luiz Andre Barroso , Mosur Kumaraswamy Ravishankar , Robert J. Stets , Daniel J. Scales
发明人： Kourosh Gharachorloo , Luiz Andre Barroso , Mosur Kumaraswamy Ravishankar , Robert J. Stets , Daniel J. Scales
IPC分类号： G06F1200
CPC分类号： G06F12/0826 , G06F12/0828 , G06F2212/621
摘要： An invalid-to-dirty request permits a transition from an invalid memory state to a dirty state without requiring an up-to-date copy of the memory. The present invention is a system for supporting invalid-to-dirty memory transactions in an aggressive cache coherence protocol that minimizes directory entry locking. The nodes of a multiprocessor system each include a protocol engine that is configured to implement a distinct invalidation request that corresponds to an invalid-to-dirty memory transaction. If node O receives this distinct invalidation request while waiting for a response to an outstanding request for exclusive ownership, the protocol engine of node O is configured to treat the distinct invalidation request as applying to the memory line of information that is the subject of the outstanding request for exclusive ownership. Furthermore, if the node O receives a normal invalidation request, while it has an outstanding exclusive request, the invalidation request applies to a previous copy of the memory line of information held by the node N and therefore the protocol engine of node O is configured to ignore the normal invalidation request in this circumstance.

2. 发明授权

US06748498B2 Scalable multiprocessor system and cache coherence method implementing store-conditional memory transactions while an associated directory entry is encoded as a coarse bit vector 失效
标题翻译：可扩展的多处理器系统和缓存一致性方法实现存储条件存储器事务，而相关联的目录条目被编码为粗位向量
公开(公告)号：US06748498B2
公开(公告)日：2004-06-08
申请号：US10042053
申请日：2002-01-07
申请人： Kourosh Gharachorloo , Luiz Andre Barroso , Mosur K. Ravishankar , Robert J. Stets , Daniel J. Scales
发明人： Kourosh Gharachorloo , Luiz Andre Barroso , Mosur K. Ravishankar , Robert J. Stets , Daniel J. Scales
IPC分类号： G06F1200
CPC分类号： G06F12/0826 , G06F12/0828 , G06F2212/621 , Y10S707/99952
摘要： A system including a plurality of processor nodes is configured to execute a cache coherence protocol that avoids the use of negative acknowledgments and ordering requirements on the underlying transaction-message interconnect/network, and implements store-conditional memory transactions. A store-conditional memory transaction succeeds if a directory tracking the state of a memory line of information unambiguously indicates that the requesting node is the exclusive owner of the memory line, if the directory ambiguously indicates that the requesting node is sharing the memory line and the requesting node is in fact sharing the memory line, or if the directory unambiguously indicates that the requesting node is sharing the memory line. The store-conditional memory transaction fails if the directory unambiguously indicates that the requesting node is not sharing the memory line, or if the directory ambiguously indicates that the requesting node may be sharing the memory line and the requesting node is in fact not sharing the memory line.
摘要翻译：包括多个处理器节点的系统被配置为执行高速缓存一致性协议，其避免对底层事务消息互连/网络使用否定确认和排序要求，并且实现存储条件存储器事务。如果跟踪存储器线的状态的目录明确地指示请求节点是存储器线的专有所有者，则存储条件存储器事务成功，如果目录模糊地指示请求节点正在共享存储器线，并且请求节点实际上共享内存线，或者如果目录明确地指示请求节点正在共享存储器线。如果目录明确地指示请求节点不共享存储器线路，或者如果目录模糊地指示请求节点可能共享存储器线且请求节点实际上不共享存储器，则存储条件存储器事务将失败线。

3. 发明授权

US06738868B2 System for minimizing directory information in scalable multiprocessor systems with logically independent input/output nodes 失效
标题翻译：用于在具有逻辑独立的输入/输出节点的可扩展多处理器系统中最小化目录信息的系统
公开(公告)号：US06738868B2
公开(公告)日：2004-05-18
申请号：US10042035
申请日：2002-01-07
申请人： Kourosh Gharachorloo , Luiz Andre Barroso , Daniel J. Scales
发明人： Kourosh Gharachorloo , Luiz Andre Barroso , Daniel J. Scales
IPC分类号： G06F1200
CPC分类号： G06F12/0826 , G06F12/0828 , G06F2212/621
摘要： A system of scalable shared-memory multiprocessors includes processor nodes and I/O nodes. The I/O nodes connect I/O devices directly to an interconnection network of a system of scalable shared-memory multiprocessors. Each node of the system includes an interface to a local memory subsystem, a memory cache and a protocol engine. The local memory subsystem stores memory lines of information and a directory. Each entry in the directory stores sharing information concerning a memory line of information stored in the local memory subsystem. The protocol engine in each I/O node is configured to limit to a predefined period of time any sharing of a memory line of information from the memory subsystem of any other node. The protocol engine in the home node of the memory line is configured to identify only nodes other than I/O nodes that are sharing the memory line of information. In one embodiment, I/O nodes that share the memory line of information are not identified in the directory entry of the memory line, and instead are represented by a count field, which indicates how many I/O nodes share the memory line of information.
摘要翻译：可扩展共享存储器多处理器的系统包括处理器节点和I / O节点。 I / O节点将I / O设备直接连接到可扩展共享存储器多处理器系统的互连网络。系统的每个节点包括到本地存储器子系统的接口，存储器高速缓存和协议引擎。本地存储器子系统存储信息的存储线和目录。目录中的每个条目存储关于存储在本地存储器子系统中的信息的存储器线的共享信息。每个I / O节点中的协议引擎被配置为限制来自任何其他节点的存储器子系统的信息的存储器线的任何共享的预定时间段。存储器线路的家庭节点中的协议引擎被配置为仅识别正在共享信息的存储器线的I / O节点之外的节点。在一个实施例中，共享存储器信息线的I / O节点不在存储器线的目录条目中标识，而是由计数字段表示，计数字段指示有多少个I / O节点共享信息的存储器线。

4. 发明授权

US06751710B2 Scalable multiprocessor system and cache coherence method 失效
标题翻译：可扩展的多处理器系统和缓存一致性方法
公开(公告)号：US06751710B2
公开(公告)日：2004-06-15
申请号：US09878982
申请日：2001-06-11
申请人： Kourosh Gharachorloo , Luiz A. Barroso , Mosur K. Ravishankar , Robert J. Stets, Jr. , Daniel J. Scales
发明人： Kourosh Gharachorloo , Luiz A. Barroso , Mosur K. Ravishankar , Robert J. Stets, Jr. , Daniel J. Scales
IPC分类号： G06F1200
CPC分类号： G06F12/0826 , G06F12/0828 , G06F2212/621
摘要： The present invention relates generally to multiprocessor computer system, and particularly to a multiprocessor system designed to be highly scalable, using efficient cache coherence logic and methodologies. More specifically, the present invention is a system and method including a plurality of processor nodes configured to execute a cache coherence protocol that avoids the use of negative acknowledgment messages (NAKs) and ordering requirements on the underlying transaction-message interconnect/network and services most 3-hop transactions with only a single visit to the home node.
摘要翻译：本发明一般涉及多处理器计算机系统，特别涉及使用有效的高速缓存一致性逻辑和方法来设计为高度可扩展的多处理器系统。更具体地说，本发明是一种包括多个处理器节点的系统和方法，所述多个处理器节点被配置为执行避免使用否定确认消息（NAK）的高速缓存一致性协议以及对底层事务 - 消息互联/网络和服务的排序要求只有一次访问家庭节点的3跳交易。

5. 发明授权

US5950228A Variable-grained memory sharing for clusters of symmetric multi-processors using private and shared state tables 失效
标题翻译：使用私有和共享状态表的对称多处理器集群的可变粒度内存共享
公开(公告)号：US5950228A
公开(公告)日：1999-09-07
申请号：US794172
申请日：1997-02-03
申请人： Daniel J. Scales , Kourosh Gharachorloo , Anshu Aggarwal
发明人： Daniel J. Scales , Kourosh Gharachorloo , Anshu Aggarwal
IPC分类号： G06F15/17 , G06F9/50 , G06F12/00 , G06F12/08 , H04L12/56 , G06F13/00
CPC分类号： H04L49/9052 , G06F12/08 , G06F12/0817 , G06F9/5016 , H04L47/6225 , H04L49/90
摘要： In a distributed shared memory system, clusters of symmetric multi-processors are connected to each other by a network. Each symmetric multi-processor includes a plurality of processors, a memory having addresses, and an input/output interface to interconnect the processors. A software implemented method enables data sharing between the clusters of symmetric multi-processors using variable sized quantities of data called blocks. A set of the addresses of the memories are designated as virtual shared addresses to store shared data, and a portion of the virtual shared addresses are allocated to store a shared data structure as one or more blocks. The size of a particular allocated block can vary for different shared data structures. Each block includes an integer number of lines, and each line includes a predetermined number of bytes of shared data. Directory information of a particular block is stored in the memory of a processor designed as the home of the block. The directory information includes the size of the particular block, the identity of the processor that last modified the data in the particular block and the identity of all processors having a copy of the block.
摘要翻译：在分布式共享存储器系统中，对称多处理器的集群通过网络相互连接。每个对称多处理器包括多个处理器，具有地址的存储器和用于互连处理器的输入/输出接口。软件实现的方法使得可以使用称为块的可变大小的数据量在对称多处理器的群集之间进行数据共享。将存储器的一组地址指定为虚拟共享地址以存储共享数据，并且分配一部分虚拟共享地址以将共享数据结构存储为一个或多个块。特定分配的块的大小可以针对不同的共享数据结构而变化。每个块包括整数行，并且每行包括预定数量的共享数据字节。特定块的目录信息被存储在设计为块的归属的处理器的存储器中。目录信息包括特定块的大小，最后修改特定块中的数据的处理器的标识以及具有该块的副本的所有处理器的标识。

6. 发明授权

US06412056B1 Extended translation lookaside buffer with fine-grain state bits 失效
标题翻译：具有细粒状态位的扩展翻译后备缓冲区
公开(公告)号：US06412056B1
公开(公告)日：2002-06-25
申请号：US08942337
申请日：1997-10-01
申请人： Kourosh Gharachorloo , Daniel J. Scales
发明人： Kourosh Gharachorloo , Daniel J. Scales
IPC分类号： G06F1210
CPC分类号： G06F12/0826 , G06F12/1027 , G06F2212/652
摘要： A software distributed shared memory system includes a translation lookaside buffer extended to include fine-grain memory block-state bits associated with each block of information within a page stored in memory. The block-state bits provide multiple block states for each block. The block-state bits are used to check the state of each block, thereby alleviating the need for software checks and reducing checking overheads associated therewith.
摘要翻译：软件分布式共享存储器系统包括翻译后备缓冲器，扩展为包括与存储在存储器中的页面内的每个信息块相关联的细粒度存储器块状态位。块状态位为每个块提供多个块状态。块状态位用于检查每个块的状态，从而减轻对软件检查的需要并减少与其相关联的检查开销。

7. 发明授权

US5933598A Method for sharing variable-grained memory of workstations by sending particular block including line and size of the block to exchange shared data structures 失效
标题翻译：通过发送包括块的行和大小的特定块来交换共享数据结构来共享工作站的可变粒度存储器的方法
公开(公告)号：US5933598A
公开(公告)日：1999-08-03
申请号：US682348
申请日：1996-07-17
申请人： Daniel J. Scales , Kourosh Gharachorloo
发明人： Daniel J. Scales , Kourosh Gharachorloo
IPC分类号： G06F9/50 , G06F13/00
CPC分类号： G06F9/5016
摘要： In a distributed shared memory system, workstations are connected to each other by a network. Each workstation includes a processor, a memory having addresses, and an input/output interface to interconnect the workstations. A software implemented method enables data sharing between the workstations using variable sized quantities of data. A set of the addresses of the memories are designated as virtual shared addresses to store shared data. A portion of the virtual shared addresses are allocated to store a shared data structure as one or more blocks. The shared data structure is accessible by programs executing in any of the processors. The size of a particular allocated block can vary for different shared data structures. Each block includes an integer number of lines, and each line includes a predetermined number of bytes of shared data. Access information of a particular block is stored in the memory of a home one of the workstations. The access information includes the size of the particular block and an identity of workstations having a copy of the block.
摘要翻译：在分布式共享存储器系统中，工作站通过网络彼此连接。每个工作站包括处理器，具有地址的存储器以及用于互连工作站的输入/输出接口。软件实现的方法使得可以使用可变大小数据的数据在工作站之间进行数据共享。一组存储器的地址被指定为虚拟共享地址以存储共享数据。虚拟共享地址的一部分被分配以将共享数据结构存储为一个或多个块。共享数据结构可由在任何处理器中执行的程序访问。特定分配的块的大小可以针对不同的共享数据结构而变化。每个块包括整数行，并且每行包括预定数量的共享数据字节。特定块的访问信息被存储在家庭工作站的存储器中。访问信息包括特定块的大小和具有该块的副本的工作站的标识。

8. 发明授权

US5787480A Lock-up free data sharing 失效
标题翻译：锁定免费数据共享
公开(公告)号：US5787480A
公开(公告)日：1998-07-28
申请号：US684281
申请日：1996-07-17
申请人： Daniel J. Scales , Kourosh Gharachorloo
发明人： Daniel J. Scales , Kourosh Gharachorloo
IPC分类号： G06F9/46 , G06F12/00
CPC分类号： G06F9/52
摘要： A software implemented method for lock-up free data sharing operates in a networked computer system including a plurality of workstations. Each workstation including a processor, a memory having addresses, and an input/output interface connected to each other by a bus. A set of addresses of the memories are designated as virtual shared addresses to store shared data. A portion of the virtual shared addresses is allocated to store the shared data as a plurality of blocks accessible by programs executing in any of the processors, each block including an integer number of lines. A program is instrumented to request an exclusive copy of the block if the program includes a store instruction which attempts to access data stored in a non-exclusive copy of the block. Additional instructions of the program are executed while the request for the exclusive copy of the block is pending. Addresses of data of the block modified by the additional instructions are recorded. In response to receiving the exclusive copy of the block, the modified data stored at the recorded addresses are merged with the data of the exclusive copy of the block.
摘要翻译：用于锁定免费数据共享的软件实现方法在包括多个工作站的联网计算机系统中运行。每个工作站包括处理器，具有地址的存储器以及通过总线彼此连接的输入/输出接口。存储器的一组地址被指定为虚拟共享地址以存储共享数据。分配虚拟共享地址的一部分以将共享数据存储为可由在任何处理器中执行的程序访问的多个块，每个块包括整数行。如果程序包括尝试访问存储在块的非排他性副本中的数据的存储指令，则程序被用来请求块的排他副本。当程序的独占副本的请求待决时，执行程序的附加指令。记录由附加指令修改的块的数据地址。响应于接收到块的独占副本，存储在记录地址处的修改数据与块的专用副本的数据合并。

9. 发明授权

US09459895B2 Virtual machine fault tolerance 有权
标题翻译：虚拟机容错
公开(公告)号：US09459895B2
公开(公告)日：2016-10-04
申请号：US13471616
申请日：2012-05-15
申请人： Ganesh Venkitachalam , Rohit Jain , Boris Weissman , Daniel J. Scales , Vyacheslav Malyugin , Jeffrey W. Sheldon , Min Xu
发明人： Ganesh Venkitachalam , Rohit Jain , Boris Weissman , Daniel J. Scales , Vyacheslav Malyugin , Jeffrey W. Sheldon , Min Xu
IPC分类号： G06F9/455 , G06F11/07
CPC分类号： G06F11/1658 , G06F9/45533 , G06F9/45558 , G06F9/4881 , G06F11/0712 , G06F11/0766 , G06F11/079 , G06F2009/45579 , G06F2009/45591 , G06F2201/805 , G06F2201/815 , G06F2201/82
摘要： In a computer system running at least a first virtual machine (VM) and a second VM on virtualization software, a computer implemented method for the second VM to provide quasi-lockstep fault tolerance for the first VM. The method includes enabling operations of the second VM to diverge from being in lockstep with operations with the first VM without resynchronizing the second VM with the first VM, if output of the second VM is not diverging from output of the first VM. The output of the second VM is compared with the output of the first VM to determine whether the output of the second VM has diverged from the output of the first VM. In response to a determination that the output of the second VM has diverged from the output of the first VM, a resynchronization of the second VM is executed.
摘要翻译：在运行虚拟化软件上的至少第一虚拟机（VM）和第二虚拟机的计算机系统中，用于所述第二虚拟机为所述第一虚拟机提供准锁步骤容错的计算机实现的方法。该方法包括如果第二VM的输出不与第一VM的输出分离，则第二VM的启用操作使得与第一VM的操作不同步，而不与第一VM重新同步第二VM。将第二VM的输出与第一VM的输出进行比较，以确定第二个VM的输出是否与第一个VM的输出分离。响应于确定第二VM的输出已经从第一VM的输出分离，执行第二VM的重新同步。

10. 发明授权

US08775696B2 Storage area network access for virtual machines 有权
标题翻译：虚拟机的存储区域网络访问
公开(公告)号：US08775696B2
公开(公告)日：2014-07-08
申请号：US13429044
申请日：2012-03-23
申请人： Daniel J. Scales , Mallik Mahalingam
发明人： Daniel J. Scales , Mallik Mahalingam
IPC分类号： G06F3/00 , G06F9/455
CPC分类号： G06F9/455 , G06F9/45558 , H04L67/1097
摘要： Techniques for enabling a virtual machine (VM) executing on a physical node to access a partition of a storage system are described. One embodiment associates an identifier with the VM for use when communicating with the storage system, wherein the identifier differs from a default identifier of a host bust adapter (HBA) usable by the physical node to communicate with the storage system.
摘要翻译：描述用于使在物理节点上执行的虚拟机（VM）访问存储系统的分区的技术。一个实施例将标识符与VM进行关联以在与存储系统通信时使用，其中标识符与物理节点可用以与存储系统通信的主机胸围适配器（HBA）的默认标识符不同。

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