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    • 2. 发明申请
    • Operational amplifier circuit and display panel driving apparatus
    • 运算放大器电路和显示面板驱动装置
    • US20100033463A1
    • 2010-02-11
    • US12461115
    • 2009-07-31
    • Kouichi NishimuraHiromichi Ohtsuka
    • Kouichi NishimuraHiromichi Ohtsuka
    • G09G5/00H03F3/45
    • H03F3/45219G09G3/3688G09G3/3696G09G2310/0291G09G2310/0297H03F3/3022H03F2203/45244H03F2203/45724
    • An operational amplifier circuit includes: an input stage for generating an internal current corresponding to a potential difference between inverting and non-inverting input terminals; and an output stage for driving an output terminal in response to the internal current. The output terminal includes: a floating current source through which the internal current flows; a PMOS transistor for driving the output terminal corresponding to a potential of a first terminal of the floating current source; and an NMOS transistor for driving the output terminal corresponding to a potential of a second terminal of the floating current source. The floating current source includes: a PMOS transistor whose source and drain are respectively connected to the first and second terminals; and an NMOS transistor whose drain and source are respectively connected to the first and second terminals. A depletion transistor is used as the latter NMOS transistor.
    • 运算放大器电路包括:输入级,用于产生对应于反相和非反相输入端之间的电位差的内部电流; 以及用于响应于内部电流驱动输出端子的输出级。 输出端子包括:内部电流流过的浮动电流源; 用于驱动对应于浮动电流源的第一端子的电位的输出端子的PMOS晶体管; 以及用于驱动对应于浮动电流源的第二端子的电位的输出端子的NMOS晶体管。 浮动电流源包括:PMOS晶体管,其源极和漏极分别连接到第一和第二端子; 以及NMOS晶体管,其漏极和源极分别连接到第一和第二端子。 耗尽晶体管用作后一个NMOS晶体管。
    • 3. 发明授权
    • Output circuit
    • 输出电路
    • US08604844B2
    • 2013-12-10
    • US13195546
    • 2011-08-01
    • Kouichi NishimuraHiromichi OhtsukaToshikazu Murata
    • Kouichi NishimuraHiromichi OhtsukaToshikazu Murata
    • H03K3/00
    • H03K19/018528
    • An output circuit includes a first output transistor disposed between a higher-potential power supply terminal and an external output terminal, a current flowing from the source of the first output transistor to the drain thereof being controlled on the basis of an external input signal; a second output transistor disposed between a lower-potential power supply terminal and the external output terminal, a current flowing from the source of the second output transistor to the drain thereof being controlled on the basis of an external input signal; and a clamping transistor having a first terminal and a control terminal, the first terminal and the control terminal being coupled to the gate of the first output transistor, and a second terminal coupled to the drain of the first output transistor.
    • 输出电路包括设置在高电位电源端子和外部输出端子之间的第一输出晶体管,基于外部输入信号控制从第一输出晶体管的源极到其漏极的电流; 设置在低电位电源端子和外部输出端子之间的第二输出晶体管,基于外部输入信号控制从第二输出晶体管的源极流向其漏极的电流; 以及具有第一端子和控制端子的钳位晶体管,所述第一端子和所述控制端子耦合到所述第一输出晶体管的栅极,以及耦合到所述第一输出晶体管的漏极的第二端子。