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1. 发明授权

US07968956B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US07968956B2
公开(公告)日：2011-06-28
申请号：US12388965
申请日：2009-02-19
申请人： Kosuke Tatsumura , Masakazu Goto , Reika Ichihara , Masato Koyama , Shigeru Kawanaka , Kazuaki Nakajima
发明人： Kosuke Tatsumura , Masakazu Goto , Reika Ichihara , Masato Koyama , Shigeru Kawanaka , Kazuaki Nakajima
IPC分类号： H01L29/78 , H01L21/70
CPC分类号： H01L21/823828 , H01L21/823842 , H01L29/785
摘要： A semiconductor device includes a semiconductor substrate, a p-channel MIS transistor formed on the substrate, the p-channel transistor having a first gate dielectric formed on the substrate and a first gate electrode layer formed on the first dielectric, and an n-channel MIS transistor formed on the substrate, the n-channel transistor having a second gate dielectric formed on the substrate and a second gate electrode layer formed on the second dielectric. A bottom layer of the first gate electrode layer in contact with the first gate dielectric and a bottom layer of the second gate electrode layer in contact with the second gate dielectric have the same orientation and the same composition including Ta and C, and a mole ratio of Ta to a total of C and Ta, (Ta/(Ta+C)), is larger than 0.5.
摘要翻译：半导体器件包括半导体衬底，形成在衬底上的p沟道MIS晶体管，形成在衬底上的第一栅极电介质的p沟道晶体管和形成在第一电介质上的第一栅极电极层，以及n沟道形成在衬底上的MIS晶体管，所述n沟道晶体管具有形成在衬底上的第二栅极电介质和形成在第二电介质上的第二栅极电极层。与第一栅极电介质接触的第一栅极电极层的底层和与第二栅极电介质接触的第二栅电极层的底层具有相同的取向和相同的组成，包括Ta和C，以及摩尔比的Ta与总计C和Ta（Ta /（Ta + C））大于0.5。

2. 发明申请

US20090267159A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20090267159A1
公开(公告)日：2009-10-29
申请号：US12388965
申请日：2009-02-19
申请人： Kosuke Tstsumura , Masakazu Goto , Reika Ichihara , Masato Koyama , Shigeru Kawanaka , Kazuaki Nakajima
发明人： Kosuke Tstsumura , Masakazu Goto , Reika Ichihara , Masato Koyama , Shigeru Kawanaka , Kazuaki Nakajima
IPC分类号： H01L27/092
CPC分类号： H01L21/823828 , H01L21/823842 , H01L29/785
摘要： A semiconductor device includes a semiconductor substrate, a p-channel MIS transistor formed on the substrate, the p-channel transistor having a first gate dielectric formed on the substrate and a first gate electrode layer formed on the first dielectric, and an n-channel MIS transistor formed on the substrate, the n-channel transistor having a second gate dielectric formed on the substrate and a second gate electrode layer formed on the second dielectric. A bottom layer of the first gate electrode layer in contact with the first gate dielectric and a bottom layer of the second gate electrode layer in contact with the second gate dielectric have the same orientation and the same composition including Ta and C, and a mole ratio of Ta to a total of C and Ta, (Ta/(Ta+C)), is larger than 0.5.
摘要翻译：半导体器件包括半导体衬底，形成在衬底上的p沟道MIS晶体管，形成在衬底上的第一栅极电介质的p沟道晶体管和形成在第一电介质上的第一栅极电极层，以及n沟道形成在衬底上的MIS晶体管，所述n沟道晶体管具有形成在衬底上的第二栅极电介质和形成在第二电介质上的第二栅极电极层。与第一栅极电介质接触的第一栅极电极层的底层和与第二栅极电介质接触的第二栅电极层的底层具有相同的取向和相同的组成，包括Ta和C，以及摩尔比的Ta与总计C和Ta（Ta /（Ta + C））大于0.5。

3. 发明授权

US08921920B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US08921920B2
公开(公告)日：2014-12-30
申请号：US13418620
申请日：2012-03-13
申请人： Shigeru Kawanaka , Kosuke Tatsumura , Naoki Yasuda , Jun Fujiki , Atsushi Kawasumi
发明人： Shigeru Kawanaka , Kosuke Tatsumura , Naoki Yasuda , Jun Fujiki , Atsushi Kawasumi
IPC分类号： H01L29/792 , H01L21/28 , G11C11/22 , G11C11/412 , G11C14/00 , H01L29/51 , H01L27/11 , H01L27/115 , H01L27/118
CPC分类号： H01L21/28282 , G11C11/22 , G11C11/412 , G11C14/0081 , H01L27/1104 , H01L27/1156 , H01L27/11568 , H01L27/11807 , H01L29/518 , H01L29/792
摘要： A semiconductor device has a semiconductor substrate, and a semiconductor element having an FET on the semiconductor substrate and comprises a different threshold voltage depending on an OFF state and an ON state. The semiconductor element has an insulating film disposed above a part where a channel of the semiconductor substrate is formed, a gate electrode disposed above the insulating film, and a charge trap film disposed between the insulating film and the gate electrode, and to exchange more electrons with the gate electrode than with the channel.
摘要翻译：半导体器件具有半导体衬底和半导体衬底上具有FET的半导体元件，并且包括根据OFF状态和ON状态的不同阈值电压。半导体元件具有设置在形成半导体基板的沟道的部分上方的绝缘膜，设置在绝缘膜上方的栅电极和设置在绝缘膜和栅电极之间的电荷陷阱膜，并且交换更多的电子栅电极与通道相比。

4. 发明申请

US20100072554A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20100072554A1
公开(公告)日：2010-03-25
申请号：US12540679
申请日：2009-08-13
申请人： Masakazu Goto , Shigeru Kawanaka
发明人： Masakazu Goto , Shigeru Kawanaka
IPC分类号： H01L27/092 , H01L29/40
CPC分类号： H01L21/823828 , H01L21/823842 , H01L27/092 , H01L29/4958 , H01L29/4966 , H01L29/517 , H01L29/518 , H01L29/7833 , H01L29/7845
摘要： A semiconductor device according to one embodiment includes: an n-type transistor comprising a first gate electrode formed on a semiconductor substrate via a first gate insulating film, a first channel region formed in the semiconductor substrate under the first gate insulating film, and first source/drain regions formed in the semiconductor substrate on both sides of the first channel region, the first gate electrode comprising a first metal layer and a first conductive layer thereon; and a p-type transistor comprising a second gate electrode formed on the semiconductor substrate via a second gate insulating film, a second channel region formed in the semiconductor substrate under the second gate insulating film, and second source/drain regions formed in the semiconductor substrate on both sides of the second channel region, the second gate electrode comprising a second metal layer and a second conductive layer thereon, the second metal layer being thicker than the first metal layer and having the same constituent element as the first metal layer.
摘要翻译：根据一个实施例的半导体器件包括：n型晶体管，包括通过第一栅极绝缘膜形成在半导体衬底上的第一栅极电极，形成在第一栅极绝缘膜下方的半导体衬底中的第一沟道区域和第一源极 /漏区，形成在第一沟道区两侧的半导体衬底中，第一栅电极包括第一金属层和第一导电层; 以及p型晶体管，包括通过第二栅极绝缘膜形成在半导体衬底上的第二栅极电极，形成在第二栅极绝缘膜下方的半导体衬底中的第二沟道区域和形成在半导体衬底中的第二源极/漏极区域在第二沟道区域的两侧，第二栅电极在其上包括第二金属层和第二导电层，第二金属层比第一金属层厚，并具有与第一金属层相同的构成元件。

5. 发明授权

US08084831B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US08084831B2
公开(公告)日：2011-12-27
申请号：US12540679
申请日：2009-08-13
申请人： Masakazu Goto , Shigeru Kawanaka
发明人： Masakazu Goto , Shigeru Kawanaka
IPC分类号： H01L27/088
CPC分类号： H01L21/823828 , H01L21/823842 , H01L27/092 , H01L29/4958 , H01L29/4966 , H01L29/517 , H01L29/518 , H01L29/7833 , H01L29/7845
摘要： A semiconductor device according to one embodiment includes: an n-type transistor comprising a first gate electrode formed on a semiconductor substrate via a first gate insulating film, a first channel region formed in the semiconductor substrate under the first gate insulating film, and first source/drain regions formed in the semiconductor substrate on both sides of the first channel region, the first gate electrode comprising a first metal layer and a first conductive layer thereon; and a p-type transistor comprising a second gate electrode formed on the semiconductor substrate via a second gate insulating film, a second channel region formed in the semiconductor substrate under the second gate insulating film, and second source/drain regions formed in the semiconductor substrate on both sides of the second channel region, the second gate electrode comprising a second metal layer and a second conductive layer thereon, the second metal layer being thicker than the first metal layer and having the same constituent element as the first metal layer.
摘要翻译：根据一个实施例的半导体器件包括：n型晶体管，包括通过第一栅极绝缘膜形成在半导体衬底上的第一栅极电极，形成在第一栅极绝缘膜下方的半导体衬底中的第一沟道区域和第一源极 /漏区，形成在第一沟道区两侧的半导体衬底中，第一栅电极包括第一金属层和第一导电层; 以及p型晶体管，包括通过第二栅极绝缘膜形成在半导体衬底上的第二栅极电极，形成在第二栅极绝缘膜下方的半导体衬底中的第二沟道区域和形成在半导体衬底中的第二源极/漏极区域在第二沟道区域的两侧，第二栅电极在其上包括第二金属层和第二导电层，第二金属层比第一金属层厚，并具有与第一金属层相同的构成元件。

6. 发明授权

US08405159B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US08405159B2
公开(公告)日：2013-03-26
申请号：US13234536
申请日：2011-09-16
申请人： Kanna Adachi , Shigeru Kawanaka , Satoshi Inaba
发明人： Kanna Adachi , Shigeru Kawanaka , Satoshi Inaba
IPC分类号： H01L27/088
CPC分类号： H01L27/1104 , H01L27/11 , H01L29/4238
摘要： In accordance with an embodiment, a semiconductor device includes an SRAM cell on a substrate. The SRAM cell includes: first and second load transistors each having an n-type source region and a p-type drain region, first and second driver transistors each having a p-type source region and an n-type drain region, and first and second transfer transistors each having an n-type source region and a n-type drain region. The n-type source regions of the first and second load transistors, the n-type drain regions of the first and second driver transistors, and the n-type source regions and the n-type drain regions of the first and second transfer transistors are located in a region other than a region present between any two of the p-type drain regions of the first and second load transistors and the p-type source regions of the first and second driver transistors.
摘要翻译：根据实施例，半导体器件在衬底上包括SRAM单元。 SRAM单元包括：具有n型源极区域和p型漏极区域的第一和第二负载晶体管，每个具有p型源极区域和n型漏极区域的第一和第二驱动器晶体管，以及第一和第二负极晶体管，第二传输晶体管，每个具有n型源极区和n型漏极区。第一和第二负载晶体管的n型源极区域，第一和第二驱动晶体管的n型漏极区域以及第一和第二转移晶体管的n型源极区域和n型漏极区域是位于除了存在于第一和第二负载晶体管的任何两个p型漏极区域之间的区域以及第一和第二驱动器晶体管的p型源极区域之外的区域中。

7. 发明申请

US20110227044A1 TRANSISTOR AND METHOD FOR MANUFACTURING THE SAME 审中-公开
标题翻译：晶体管及其制造方法
公开(公告)号：US20110227044A1
公开(公告)日：2011-09-22
申请号：US13046940
申请日：2011-03-14
申请人： Shigeru Kawanaka , Kanna Adachi , Toshitaka Miyata , Hideji Tsujii
发明人： Shigeru Kawanaka , Kanna Adachi , Toshitaka Miyata , Hideji Tsujii
IPC分类号： H01L29/08 , B82Y99/00
CPC分类号： H01L29/78684 , B82Y10/00 , H01L29/1606 , H01L29/41733 , H01L29/41775 , H01L29/45 , H01L29/778 , H01L29/7839
摘要： In one embodiment, a transistor includes: a substrate; a source electrode formed on the substrate; a drain electrode formed on the substrate; a graphene film formed between the source electrode and the drain electrode, the graphene film having a semiconductor region including a source side end and a conductor region including a drain side end, a width of the source side end of the graphene film in a channel width direction being narrower than a width of the drain side end of the graphene film in the channel width direction; and a gate electrode formed via a gate insulating film on the semiconductor region of the graphene film and the conductor region of the graphene film. The source electrode is connected to the source side end of the graphene film with a Schottky contact, and the drain electrode is connected to the drain side end of the graphene film with an ohmic contact.
摘要翻译：在一个实施例中，晶体管包括：衬底; 形成在所述基板上的源电极; 形成在所述基板上的漏电极; 形成在源电极和漏电极之间的石墨烯膜，所述石墨烯膜具有包括源极侧端部和包括漏极侧端部的导体区域的半导体区域，所述石墨烯膜的源极侧端部的宽度在沟道宽度方向比通道宽度方向上的石墨烯膜的漏极侧端部的宽度窄; 以及在石墨烯膜的半导体区域和石墨烯膜的导体区域上经由栅极绝缘膜形成的栅电极。源电极以肖特基接触连接到石墨烯膜的源侧端，并且漏电极以欧姆接触连接到石墨烯膜的漏极侧端。

8. 发明申请

US20060157738A1 Semiconductor memory device and its manufacturing method 审中-公开
公开(公告)号：US20060157738A1
公开(公告)日：2006-07-20
申请号：US11369041
申请日：2006-03-07
申请人： Shigeru Kawanaka
发明人： Shigeru Kawanaka
IPC分类号： H01L27/10
CPC分类号： H01L21/84 , G11C11/405 , H01L27/108 , H01L27/11 , H01L27/1203 , H01L29/7841
摘要： According to one aspect of the present invention, a semiconductor memory device has: a semiconductor layer formed on an insulating film; and a memory cell array including a matrix arrangement of a plurality of memory cells each made up of first and second transistors connected in series, one side of each memory cell being connected to a bit line and the other side of each memory cell being supplied with a reference potential, and according to another aspect of the present invention, a semiconductor memory device manufacturing method includes: forming an oxide layer and a silicon active layer on a semiconductor substrate; forming an element isolation region for separating said silicon active layer into discrete element-forming regions to be substantially flush with said silicon active layer; forming gate electrode of paired two transistors by depositing a gate electrode material on said silicon active layer and patterning it; injecting predetermined ions into a region for forming a diffusion layer in, using said gate electrodes as an ion injection mask; forming said paired transistors by activating the injected ions through a heat process; and forming a first gate line connected to the gate electrode of one of said paired transistors and a second gate line connected to the gate electrode of the other of said paired transistors.

9. 发明授权

US06576956B2 Semiconductor integrated circuit and method of manufacturing the same 失效
公开(公告)号：US06576956B2
公开(公告)日：2003-06-10
申请号：US09902700
申请日：2001-07-12
申请人： Shigeru Kawanaka
发明人： Shigeru Kawanaka
IPC分类号： H01L2701
CPC分类号： H01L27/1203 , H01L21/84 , H03K19/0948
摘要： A multi-input logic circuit (e.g. a 2-input NAND circuit) mounted on a semiconductor integrated circuit comprises a plurality of voltage-activated transistors which have the same channel conduction type and are electrically connected in series between a power supply terminal and an output terminal. A source region and a body region of at least the voltage-activated transistor connected to the output terminal are electrically connected and have substantially the same potential. The semiconductor integrated circuit has either an SOI or SOS structure.

10. 发明申请

US20120228706A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20120228706A1
公开(公告)日：2012-09-13
申请号：US13358643
申请日：2012-01-26
申请人： Emiko Sugizaki , Shigeru Kawanaka , Kanna Adachi
发明人： Emiko Sugizaki , Shigeru Kawanaka , Kanna Adachi
IPC分类号： H01L29/78
CPC分类号： H01L29/7391 , H01L29/0657 , H01L29/42312
摘要： A memory includes a semiconductor layer, a gate insulating film on the semiconductor layer, and a gate electrode on the gate insulating film. A first channel region of a first conductivity type is provided on a surface of the semiconductor layer below the gate insulating film. A diffusion layer of a second conductivity type is provided below the first channel region in the semiconductor layer. The diffusion layer contacts a bottom of the first channel region in a direction substantially vertical to a surface of the semiconductor layer. The diffusion layer forms a PN junction with the bottom of the first channel region. A drain of a first conductivity type and a source of a second conductivity type are provided on a side and another side of the first channel region. A sidewall film covers a side surface of the first channel region on a side of the diffusion layer.
摘要翻译：存储器包括半导体层，半导体层上的栅极绝缘膜和栅极绝缘膜上的栅电极。第一导电类型的第一沟道区设置在栅极绝缘膜下方的半导体层的表面上。第二导电类型的扩散层设置在半导体层中的第一沟道区的下方。扩散层在与半导体层的表面大致垂直的方向上接触第一沟道区的底部。扩散层与第一通道区域的底部形成PN结。第一导电类型的漏极和第二导电类型的源极设置在第一沟道区的一侧和另一侧。侧壁膜覆盖扩散层侧的第一沟道区域的侧表面。

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