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1. 发明授权

US6057229A Method for metallizing submicron contact holes in semiconductor bodies 失效
标题翻译：在半导体器件中金属化亚微米接触孔的方法
公开(公告)号：US6057229A
公开(公告)日：2000-05-02
申请号：US828677
申请日：1997-03-31
申请人： Konrad Hieber , Helmuth Treichel , Heinrich Koerner
发明人： Konrad Hieber , Helmuth Treichel , Heinrich Koerner
IPC分类号： C23C16/06 , H01L21/28 , H01L21/285 , H01L21/3205 , H01L21/768 , H01L23/485 , H01L23/52 , H01L29/45 , H01L21/4763
CPC分类号： H01L21/76865 , H01L21/76843 , H01L21/76877 , H01L23/485 , H01L29/456 , H01L2924/0002 , H01L2924/3011 , Y10S438/907 , Y10S438/908
摘要： Submicron contact holes in semiconductor bodies are metalized in a single operation. A titanium-rich layer is first deposited, which is followed by a low-resistance TiSi.sub.2 layer. The two layers are thus deposited in one contiguous CVD process inside a single CVD chamber.
摘要翻译：半导体体中的亚微米接触孔在一次操作中被金属化。首先沉积富钛层，其后是低电阻TiSi 2层。因此，这两层沉积在单个CVD室内的一个连续的CVD工艺中。

2. 发明授权

US5478780A Method and apparatus for producing conductive layers or structures for VLSI circuits 失效
标题翻译：用于生产VLSI电路的导电层或结构的方法和装置
公开(公告)号：US5478780A
公开(公告)日：1995-12-26
申请号：US851245
申请日：1992-03-13
申请人： Heinrich Koerner , Helmuth Treichel , Konrad Hieber , Peter Kuecher
发明人： Heinrich Koerner , Helmuth Treichel , Konrad Hieber , Peter Kuecher
IPC分类号： H01L21/285 , H01L21/283
CPC分类号： H01L21/28512 , Y10S438/908
摘要： Methods and apparatus for producing conductive layers or structures for VLSI circuits. In a method for producing conductive layers or structures for VLSI circuits, at least two method stages are implemented in direct succession in different chambers of a high-vacuum system without interrupting the high-vacuum conditions for the semiconductor substrate. Avoiding exposure to air between the method stages produces noticeably improved layer properties and enables particularly simple and reliable multi-stage methods for producing conductive layers that promote a multi-layer wiring on the semiconductor substrate. An apparatus for implementing the method has a plurality of high-vacuum process chambers, at least one high-vacuum distributor chamber connecting the process chambers and of at least two high-vacuum supply chambers for semiconductor substrates.
摘要翻译：用于生产VLSI电路的导电层或结构的方法和装置。在用于制造用于VLSI电路的导电层或结构的方法中，至少两个方法阶段直接连续地在高真空系统的不同室中实现，而不中断半导体衬底的高真空条件。避免在方法阶段之间暴露于空气中产生明显改善的层性质，并且能够实现特别简单可靠的多级方法来产生促进半导体衬底上的多层布线的导电层。用于实施该方法的装置具有多个高真空处理室，连接处理室和至少两个用于半导体基板的高真空供应室的至少一个高真空分配器室。

3. 发明授权

US08643183B2 Long-term heat-treated integrated circuit arrangements and methods for producing the same 有权
标题翻译：长期热处理集成电路布置及其制造方法
公开(公告)号：US08643183B2
公开(公告)日：2014-02-04
申请号：US11589349
申请日：2006-10-30
申请人： Oliver Aubel , Wolfgang Hasse , Martina Hommel , Heinrich Koerner
发明人： Oliver Aubel , Wolfgang Hasse , Martina Hommel , Heinrich Koerner
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L21/76864 , H01L21/76843 , H01L21/76844 , H01L21/76849 , H01L21/76852 , H01L21/76858 , H01L21/76865 , H01L21/76867 , H01L21/76877 , H01L21/76885 , H01L21/76886 , H01L23/5226 , H01L23/53238 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： An explanation is given of, inter alia, methods in which the barrier material is removed at a via bottom or at a via top area by long-term heat treatment. Concurrently or alternatively, interconnects are coated with barrier material in a simple and uncomplicated manner by means of the long-term heat treatment.
摘要翻译：特别地说明了通过长期热处理在通孔底部或通孔顶部区域去除阻挡材料的方法。同时或替代地，互连通过长期热处理以简单且不复杂的方式涂覆有阻挡材料。

4. 发明申请

US20120258594A1 On-Chip RF Shields with Backside Redistribution Lines 有权
标题翻译：带背面再分配线的片上RF屏蔽
公开(公告)号：US20120258594A1
公开(公告)日：2012-10-11
申请号：US13084105
申请日：2011-04-11
申请人： Hans-Joachim Barth , Jens Pohl , Gottfried Beer , Heinrich Koerner
发明人： Hans-Joachim Barth , Jens Pohl , Gottfried Beer , Heinrich Koerner
IPC分类号： H01L21/28
CPC分类号： H01L21/76898 , H01L21/3065 , H01L21/308 , H01L21/76879 , H01L23/481 , H01L23/552 , H01L23/66 , H01L2223/6688 , H01L2224/02372 , H01L2224/0401 , H01L2224/05008 , H01L2224/05569 , H01L2924/00014 , H01L2224/05552
摘要： Structures of a system on chip and methods of forming a system on chip are disclosed. In one embodiment, a method of fabricating the system on chip includes forming a through substrate opening from a back surface of a substrate, the through substrate opening disposed between a first and a second region, the first region comprising devices for RF circuitry and the second region comprising devices for other circuitry. The method further includes forming patterns for redistribution lines on a photo resist layer, the photo resist layer disposed under the back surface, and filling the through substrate opening and the patterns for redistribution lines with a conductive material.
摘要翻译：公开了一种片上系统的结构以及片上系统的形成方法。在一个实施例中，一种制造片上系统的方法包括从衬底的背面形成穿透衬底开口，穿过衬底开口设置在第一和第二区域之间，第一区域包括用于RF电路的装置，第二区域包括第二区域包括用于其他电路的装置。该方法还包括在光致抗蚀剂层上形成用于再分配线的图案，设置在背面下方的光致抗蚀剂层，以及用导电材料填充贯通基板开口和再分配线图案。

5. 发明申请

US20120045893A1 METHOD OF MAKING INTERCONNECT STRUCTURE 有权
标题翻译：制造互连结构的方法
公开(公告)号：US20120045893A1
公开(公告)日：2012-02-23
申请号：US13285007
申请日：2011-10-31
申请人： Heinrich Koerner
发明人： Heinrich Koerner
IPC分类号： H01L21/768
CPC分类号： H01L23/53252 , H01L21/28512 , H01L21/76807 , H01L21/76826 , H01L21/76843 , H01L21/76846 , H01L21/76873 , H01L23/485 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： One or more embodiments relate to a method of forming a semiconductor device having a substrate, comprising: providing a Si-containing layer; forming a barrier layer over the Si-containing layer, the barrier layer comprising a compound including a metallic element; forming a metallic nucleation_seed layer over the Si-containing layer, the nucleation_seed layer including the metallic element; and forming a metallic interconnect layer over the nucleation_seed layer, wherein the barrier layer and the nucleation_seed layer are formed without exposing the semiconductor device substrate to the ambient atmosphere.
摘要翻译：一个或多个实施方案涉及形成具有基底的半导体器件的方法，包括：提供含Si层; 在所述含Si层上形成阻挡层，所述阻挡层包括包含金属元素的化合物; 在所述含Si层上形成金属成核层，所述成核层包括所述金属元素; 以及在成核层上形成金属互连层，其中形成阻挡层和成核层，而不将半导体器件衬底暴露于环境气氛。

6. 发明授权

US08049336B2 Interconnect structure 有权
标题翻译：互连结构
公开(公告)号：US08049336B2
公开(公告)日：2011-11-01
申请号：US12241083
申请日：2008-09-30
申请人： Heinrich Koerner
发明人： Heinrich Koerner
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L23/53252 , H01L21/28512 , H01L21/76807 , H01L21/76826 , H01L21/76843 , H01L21/76846 , H01L21/76873 , H01L23/485 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： One or more embodiments relate to a semiconductor device, comprising: a Si-containing layer; a barrier layer disposed over the Si-containing layer, the barrier layer comprising a compound including a metallic element; a metallic nucleation_seed layer disposed over the barrier layer, the nucleation_seed layer including the metallic element; and a metallic interconnect layer disposed over the nucleation_seed layer, the interconnect layer comprising at least one element selected from the group consisting of Cu (copper), Au (gold), and Ag (silver).
摘要翻译：一个或多个实施例涉及半导体器件，包括：含Si层; 设置在所述含Si层上的阻挡层，所述阻挡层包括包含金属元素的化合物; 设置在所述阻挡层上的金属成核层，所述成核层包括所述金属元素; 以及设置在成核层上的金属互连层，所述互连层包括选自Cu（铜），Au（金）和Ag（银）中的至少一种元素。

7. 发明授权

US07936052B2 On-chip RF shields with backside redistribution lines 有权
标题翻译：具有背面再分配线的片上RF屏蔽
公开(公告)号：US07936052B2
公开(公告)日：2011-05-03
申请号：US12242487
申请日：2008-09-30
申请人： Hans-Joachim Barth , Jens Pohl , Gottfried Beer , Heinrich Koerner
发明人： Hans-Joachim Barth , Jens Pohl , Gottfried Beer , Heinrich Koerner
IPC分类号： H01L29/72
CPC分类号： H01L21/76898 , H01L23/3114 , H01L23/481 , H01L23/552 , H01L2224/02372 , H01L2224/0401 , H01L2224/05 , H01L2224/05569 , H01L2924/0002 , H01L2224/05552
摘要： Structures of a system on chip and methods of forming a system on chip are disclosed. In one embodiment, a method of fabricating the system on chip includes forming a through substrate opening from a back surface of a substrate, the through substrate opening disposed between a first and a second region, the first region comprising devices for RF circuitry and the second region comprising devices for other circuitry. The method further includes forming patterns for redistribution lines on a photo resist layer, the photo resist layer disposed under the back surface, and filling the through substrate opening and the patterns for redistribution lines with a conductive material.
摘要翻译：公开了一种片上系统的结构以及片上系统的形成方法。在一个实施例中，一种制造片上系统的方法包括从衬底的背面形成穿透衬底开口，穿过衬底开口设置在第一和第二区域之间，第一区域包括用于RF电路的装置，第二区域包括第二区域包括用于其他电路的装置。该方法还包括在光致抗蚀剂层上形成用于再分配线的图案，设置在背面下方的光致抗蚀剂层，以及用导电材料填充贯通基板开口和再分配线图案。

8. 发明授权

US07656037B2 Integrated circuit with improved component interconnections 有权
标题翻译：具有改进的组件互连的集成电路
公开(公告)号：US07656037B2
公开(公告)日：2010-02-02
申请号：US11525113
申请日：2006-09-21
申请人： Martina Hommel , Heinrich Koerner , Markus Schwerd , Martin Seck
发明人： Martina Hommel , Heinrich Koerner , Markus Schwerd , Martin Seck
IPC分类号： H01S5/00 , H01S3/13 , H01L23/52 , H01L23/522 , H01L27/08 , H01L23/64
CPC分类号： H01L23/5227 , H01L23/5225 , H01L23/60 , H01L2223/6622 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： An integrated circuit arrangement is disclosed. In one embodiment, the integrated circuit arrangement includes at least three conductive structures levels and elongated interconnects.
摘要翻译：公开了一种集成电路装置。在一个实施例中，集成电路装置包括至少三个导电结构层和细长互连。

9. 发明申请

US20060267205A1 Integrated circuit arrangement with layer stack, and process 有权
标题翻译：集成电路布置与层叠，和过程
公开(公告)号：US20060267205A1
公开(公告)日：2006-11-30
申请号：US11438080
申请日：2006-05-19
申请人： Heinrich Koerner
发明人： Heinrich Koerner
IPC分类号： H01L23/48 , H01L23/52
CPC分类号： H01L23/53238 , H01L21/76846 , H01L21/76856 , H01L21/76873 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit arrangement includes an electrically conductive conduction structure made from copper or a copper alloy. At a side wall of the conduction structure, there is a layer stack which includes at least three layers. Despite very thin layers in the layer stack, it is possible to achieve a high barrier action against copper diffusion combined with a high electrical conductivity, as is required for electrolytic deposition of copper using external current.
摘要翻译：集成电路装置包括由铜或铜合金制成的导电导电结构。在导电结构的侧壁处，存在包括至少三层的层叠层。尽管层叠中的层非常薄，但是可以实现与铜电极扩散相结合的高导电性的高屏障作用，如使用外部电流的铜电解沉积所需要的。

10. 发明申请

US20120149168A1 Process for Producing a Multifunctional Dielectric Layer on a Substrate 审中-公开
标题翻译：在基板上制造多功能介电层的工艺
公开(公告)号：US20120149168A1
公开(公告)日：2012-06-14
申请号：US13402890
申请日：2012-02-23
申请人： Johann Helneder , Markus Schwerd , Thomas Goebel , Andrea Mitchell , Heinrich Koerner , Martina Hommel
发明人： Johann Helneder , Markus Schwerd , Thomas Goebel , Andrea Mitchell , Heinrich Koerner , Martina Hommel
IPC分类号： H01L21/768 , H01L21/02
CPC分类号： H01L23/53238 , C23C14/22 , C23C16/44 , H01L21/76834 , H01L21/76888 , H01L23/5228 , H01L23/53223 , H01L2924/0002 , H01L2924/00
摘要： A multifunctional dielectric layer can be formed on a substrate, especially on an exposed metallic strip conductor system on a substrate. An additional metal layer is formed across the surface of the exposed metal strip conductors. The metal layer is then at least partially converted to a nonconducting metal oxide, the dielectric layer.
摘要翻译：可以在基板上形成多功能电介质层，特别是在基板上的露出的金属带状导体系上。在暴露的金属带状导体的表面上形成另外的金属层。然后将金属层至少部分地转变成不导电的金属氧化物，介电层。

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