会员体验
专利管家(专利管理)
工作空间(专利管理)
风险监控(情报监控)
数据分析(专利分析)
侵权分析(诉讼无效)
联系我们
交流群
官方交流:
QQ群: 891211   
微信请扫码    >>>
现在联系顾问~
热词
    • 2. 发明授权
    • Method of manufacturing semiconductor device with a tunnel diode
    • 制造具有隧道二极管的半导体器件的方法
    • US6436785B2
    • 2002-08-20
    • US83272401
    • 2001-04-11
    • KONINKL PHILIPS ELECTRONICS NV
    • BROWN ADAM RHURKX GODEFRIDUS A MDE BOER WIEBE BSLOTBOOM JAN W
    • H01L29/866H01L29/24H01L29/885H01L21/20
    • H01L29/885Y10S438/979
    • A semiconductor device with a tunnel diode comprises two mutually adjoining semiconductor regions (2, 3) of opposed conductivity types having high enough doping concentrations to provide a tunneling junction. Portions (2A, 3A) of the semiconductor regions adjoining the junction comprise a mixed crystal of silicon and germanium. The doping concentration of both phosphorus and boron are substantially increased, given the same amount of dopants being offered as during the formation of the remainder of the regions. The tunneling efficiency is substantially improved, and also because of the reduced bandgap of said portions (2A, 3A). A much steeper current-voltage characteristic both in the forward and in the reverse direction is achieved. Thus, the tunneling pn junction can be used as a transition between two conventional diodes which are stacked one on the other and formed in a single epitaxial growing process. The doping concentration may be 6x1019 or even more than 1020 at/cm3. A simple method of manufacturing such a device is preferably done at a temperature between 550° C. and 800° C.
    • 具有隧道二极管的半导体器件包括具有足够高掺杂浓度的相对导电类型的两个相互邻接的半导体区域(2,3)以提供隧道结。 邻接连接处的半导体区域的部分(2A,3A)包括硅和锗的混合晶体。 给定与在其余区域形成期间相同量的掺杂剂,磷和硼的掺杂浓度显着增加。 隧道效率显着提高,并且还因为所述部分(2A,3A)的带隙减小。 实现了在正向和反向方向上更陡峭的电流 - 电压特性。 因此,隧道pn结可以用作两个常规二极管之间的过渡,这两个二极管彼此堆叠并且以单个外延生长工艺形成。 掺杂浓度可以为6×1019或甚至高于1020 at / cm3。 制造这种器件的简单方法优选在550℃和800℃之间的温度下进行。
    • 3. 发明申请
    • CONTROLLING PARASITIC BIPOLAR GAIN IN A CMOS DEVICE
    • 在CMOS器件中控制PARASITIC BIPOLAR GAIN
    • WO2006040720A3
    • 2006-07-06
    • PCT/IB2005053308
    • 2005-10-10
    • KONINKL PHILIPS ELECTRONICS NVAGARWAL PRABHATSLOTBOOM JAN W
    • AGARWAL PRABHATSLOTBOOM JAN W
    • H01L27/092H01L29/08
    • H01L27/0921
    • A CMOS device comprising an n-channel MOS transistor (102) and a p­channel MOS transistor (100), defining a pair of parasitic bipolar transitors (110a, 110b) therebetween, wherein a layer (120) of doped SiGe is provided over the source region (106a) of at least one of the MOS transistors (100, 102), between the source region (106a) and the source contact (122). The layer (120) of material acts as a sink for minority carriers (holes in an N-type device) at the source, which has the effect of increasing surface recombination velocity (because the landgap of SiGe is lower than that of the Si substrate (104)), which, in turn, lowers the current gain of the respective parasitic bipolar device. As a result, the effects and/or occurrence of latch-up, and other breakdown instabilities associated with parasitic bipolar devices, can be limited.
    • 一种CMOS器件,包括n沟道MOS晶体管(102)和沟道MOS晶体管(100),其间限定了一对寄生双极性交变器(110a,110b),其中掺杂的SiGe层(120)设置在源极 在所述源极区域(106a)和所述源极触点(122)之间的至少一个所述MOS晶体管(100,102)的区域(106a)。 材料层(120)作为源极上的少数载流子(N型器件中的空穴)的吸收器,具有增加表面复合速度的作用(因为SiGe的边界低于Si衬底的边界 (104)),这又降低了相应寄生双极器件的电流增益。 结果,可以限制与寄生双极器件相关联的闩锁和其他击穿不稳定性的效果和/或发生。