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1. 发明授权

US07675076B2 Nitride-based semiconductor device of reduced voltage drop 有权
标题翻译：氮化物半导体器件降低电压降
公开(公告)号：US07675076B2
公开(公告)日：2010-03-09
申请号：US11375964
申请日：2006-03-15
申请人： Koji Otsuka , Tetsuji Moku , Junji Sato , Yoshiki Tada , Takashi Yoshida
发明人： Koji Otsuka , Tetsuji Moku , Junji Sato , Yoshiki Tada , Takashi Yoshida
IPC分类号： H01L33/00
CPC分类号： H01L29/267 , H01L21/02381 , H01L21/02458 , H01L21/02507 , H01L21/0254 , H01L21/02576 , H01L21/02579 , H01L21/0262 , H01L29/2003 , H01L33/007
摘要： A light-emitting device has a main semiconductor region formed via an n-type AlInGaN buffer region on a p-type silicon substrate, the latter being sufficiently electroconductive to provide part of the current path through the device. Constituting the primary working part of the LED, the main semiconductor region comprises an n-type GaN layer, an active layer, and a p-type GaN layer, which are successively epitaxially grown in that order on the buffer region. A heterojunction is created between p-type substrate and n-type buffer region. Carrier transportation from substrate to buffer region is expedited by the interface levels of the heterojunction, with a consequent reduction of the drive voltage requirement of the LED.
摘要翻译：发光器件具有通过p型硅衬底上的n型AlInGaN缓冲区形成的主半导体区域，该半导体区域充分导电以提供穿过器件的电流路径的一部分。构成LED的初级工作部分，主半导体区域包括依次在缓冲区上外延生长的n型GaN层，有源层和p型GaN层。在p型衬底和n型缓冲区之间产生异质结。从衬底到缓冲区域的载流子传输通过异质结的界面水平加速，从而降低了LED的驱动电压要求。

2. 发明申请

US20060175628A1 Nitride-based semiconductor device of reduced voltage drop, and method of fabrication 有权
标题翻译：降低电压降的氮化物半导体器件及其制造方法
公开(公告)号：US20060175628A1
公开(公告)日：2006-08-10
申请号：US11378963
申请日：2006-03-17
申请人： Koji Otsuka , Tetsuji Moku , Junji Sato , Yoshiki Tada , Takashi Yoshida
发明人： Koji Otsuka , Tetsuji Moku , Junji Sato , Yoshiki Tada , Takashi Yoshida
IPC分类号： H01L33/00 , H01L21/00
CPC分类号： H01L29/267 , H01L21/02381 , H01L21/02458 , H01L21/02507 , H01L21/0254 , H01L21/02576 , H01L21/02579 , H01L21/0262 , H01L29/2003 , H01L33/007
摘要： A light-emitting diode is built on a silicon substrate which has been doped with a p-type impurity to possess sufficient conductivity to provide part of the current path through the LED. The p-type silicon substrate has epitaxially grown thereon a buffer region of n-type AlInGaN. Further grown epitaxially on the buffer region is the main semiconductor region of the LED which comprises a lower confining layer of n-type GaN, an active layer for generating light, and an upper confining layer of p-type GaN. In the course of the growth of the buffer region and main semiconductor region there occurs a thermal diffusion of gallium and other Group III elements from the buffer region into the p-type silicon substrate, with the consequent creation of a p-type low-resistance region in the substrate. Interface levels are created across the heterojunction between p-type silicon substrate and n-type buffer region. The interface levels expedite carrier transport from substrate to buffer region, contributing to reduction of the drive voltage requirement of the LED.
摘要翻译：在已经掺杂有p型杂质的硅衬底上建立发光二极管以具有足够的导电性以提供通过LED的电流路径的一部分。 p型硅衬底在其上外延生长n型AlInGaN的缓冲区。在缓冲区域外延生长的是LED的主要半导体区域，其包括n型GaN的下约束层，用于产生光的有源层和p型GaN的上部约束层。在缓冲区和主半导体区域的生长过程中，发生镓和其他III族元素从缓冲区到p型硅衬底的热扩散，随之产生p型低电阻区域。在p型硅衬底和n型缓冲区之间的异质结上形成界面电平。接口电平加快了从衬底到缓冲区域的载流子传输，有助于降低LED的驱动电压要求。

3. 发明授权

US07671375B2 Nitride-based semiconductor device of reduced voltage drop, and method of fabrication 有权
标题翻译：降低电压降的氮化物半导体器件及其制造方法
公开(公告)号：US07671375B2
公开(公告)日：2010-03-02
申请号：US11378963
申请日：2006-03-17
申请人： Koji Otsuka , Tetsuji Moku , Junji Sato , Yoshiki Tada , Takashi Yoshida
发明人： Koji Otsuka , Tetsuji Moku , Junji Sato , Yoshiki Tada , Takashi Yoshida
IPC分类号： H01L33/00
CPC分类号： H01L29/267 , H01L21/02381 , H01L21/02458 , H01L21/02507 , H01L21/0254 , H01L21/02576 , H01L21/02579 , H01L21/0262 , H01L29/2003 , H01L33/007
摘要： A light-emitting diode is built on a silicon substrate which has been doped with a p-type impurity to possess sufficient conductivity to provide part of the current path through the LED. The p-type silicon substrate has epitaxially grown thereon a buffer region of n-type AlInGaN. Further grown epitaxially on the buffer region is the main semiconductor region of the LED which comprises a lower confining layer of n-type GaN, an active layer for generating light, and an upper confining layer of p-type GaN. In the course of the growth of the buffer region and main semiconductor region there occurs a thermal diffusion of gallium and other Group III elements from the buffer region into the p-type silicon substrate, with the consequent creation of a p-type low-resistance region in the substrate. Interface levels are created across the heterojunction between p-type silicon substrate and n-type buffer region. The interface levels expedite carrier transport from substrate to buffer region, contributing to reduction of the drive voltage requirement of the LED.
摘要翻译：在已经掺杂有p型杂质的硅衬底上建立发光二极管以具有足够的导电性以提供通过LED的电流路径的一部分。 p型硅衬底在其上外延生长n型AlInGaN的缓冲区。在缓冲区域外延生长的是LED的主要半导体区域，其包括n型GaN的下约束层，用于产生光的有源层和p型GaN的上部约束层。在缓冲区和主半导体区域的生长过程中，发生镓和其他III族元素从缓冲区到p型硅衬底的热扩散，随之产生p型低电阻区域。在p型硅衬底和n型缓冲区之间的异质结上形成界面电平。接口电平加快了从衬底到缓冲区域的载流子传输，有助于降低LED的驱动电压要求。

4. 发明授权

US07400000B2 Nitride-based semiconductor device 有权
标题翻译：氮化物半导体器件
公开(公告)号：US07400000B2
公开(公告)日：2008-07-15
申请号：US11294510
申请日：2005-12-05
申请人： Koji Otsuka , Junji Sato , Tetsuji Moku , Yoshiki Tada , Takashi Yoshida
发明人： Koji Otsuka , Junji Sato , Tetsuji Moku , Yoshiki Tada , Takashi Yoshida
IPC分类号： H01L31/0328
CPC分类号： H01L33/12 , H01L21/02381 , H01L21/02458 , H01L21/02491 , H01L21/02505 , H01L21/02507 , H01L21/0254 , H01L21/0262 , H01L29/2003 , H01L29/7371 , H01L33/14
摘要： A light-emitting diode is built on a silicon substrate doped with a p-type impurity to possess sufficient conductivity to provide a current path. The p-type silicon substrate has epitaxially grown thereon two superposed buffer layers of aluminum nitride and n-type indium gallium nitride. Further grown epitaxially on the buffer layers is the main semiconductor region of the LED which comprises a lower confining layer of n-type gallium nitride, an active layer for generating light, and an upper confining layer of p-type gallium nitride. In the course of the growth of the main semiconductor region there occurs a thermal diffusion of aluminum, gallium and indium from the buffer layers into the p-type silicon substrate, with the consequent creation of an alloy layer of the diffused metals. Representing p-type impurities in the p-type silicon substrate, these metals do not create a pn junction in the substrate which causes a forward voltage drop.
摘要翻译：在掺杂有p型杂质的硅衬底上建立发光二极管以具有足够的导电性以提供电流路径。 p型硅衬底在其上外延生长氮化铝和n型氮化铟镓的叠加缓冲层。在缓冲层上外延生长的是LED的主要半导体区域，其包括n型氮化镓的下约束层，用于产生光的有源层和p型氮化镓的上约束层。在主半导体区域的生长过程中，铝，镓和铟从缓冲层发生热扩散到p型硅衬底中，随之产生扩散金属的合金层。在p型硅衬底中表示p型杂质，这些金属在衬底中不产生引起正向压降的pn结。

5. 发明申请

US20060157730A1 Nitride-based semiconductor device of reduced voltage drop 有权
标题翻译：氮化物半导体器件降低电压降
公开(公告)号：US20060157730A1
公开(公告)日：2006-07-20
申请号：US11375964
申请日：2006-03-15
申请人： Koji Otsuka , Tetsuji Moku , Junji Sato , Yoshiki Tada , Takashi Yoshida
发明人： Koji Otsuka , Tetsuji Moku , Junji Sato , Yoshiki Tada , Takashi Yoshida
IPC分类号： H01L33/00
CPC分类号： H01L29/267 , H01L21/02381 , H01L21/02458 , H01L21/02507 , H01L21/0254 , H01L21/02576 , H01L21/02579 , H01L21/0262 , H01L29/2003 , H01L33/007
摘要： A light-emitting device has a main semiconductor region formed via an n-type AlInGaN buffer region on a p-type silicon substrate, the latter being sufficiently electroconductive to provide part of the current path through the device. Constituting the primary working part of the LED, the main semiconductor region comprises an n-type GaN layer, an active layer, and a p-type GaN layer, which are successively epitaxially grown in that order on the buffer region. A heterojunction is created between p-type substrate and n-type buffer region. Carrier transportation from substrate to buffer region is expedited by the interface levels of the heterojunction, with a consequent reduction of the drive voltage requirement of the LED.
摘要翻译：发光器件具有通过p型硅衬底上的n型AlInGaN缓冲区形成的主半导体区域，该半导体区域充分导电以提供穿过器件的电流路径的一部分。构成LED的初级工作部分，主半导体区域包括依次在缓冲区上外延生长的n型GaN层，有源层和p型GaN层。在p型衬底和n型缓冲区之间产生异质结。从衬底到缓冲区域的载流子传输通过异质结的界面水平加速，从而降低了LED的驱动电压要求。

6. 发明申请

US20060094145A1 Nitride-based semiconductor device and method of fabrication 有权
标题翻译：基于氮化物的半导体器件及其制造方法
公开(公告)号：US20060094145A1
公开(公告)日：2006-05-04
申请号：US11294510
申请日：2005-12-05
申请人： Koji Otsuka , Junji Sato , Tetsuji Moku , Yoshiki Tada , Takashi Yoshida
发明人： Koji Otsuka , Junji Sato , Tetsuji Moku , Yoshiki Tada , Takashi Yoshida
IPC分类号： H01L21/00
CPC分类号： H01L33/12 , H01L21/02381 , H01L21/02458 , H01L21/02491 , H01L21/02505 , H01L21/02507 , H01L21/0254 , H01L21/0262 , H01L29/2003 , H01L29/7371 , H01L33/14
摘要： A light-emitting diode is built on a silicon substrate doped with a p-type impurity to possess sufficient conductivity to provide a current path. The p-type silicon substrate has epitaxially grown thereon two superposed buffer layers of aluminum nitride and n-type indium gallium nitride. Further grown epitaxially on the buffer layers is the main semiconductor region of the LED which comprises a lower confining layer of n-type gallium nitride, an active layer for generating light, and an upper confining layer of p-type gallium nitride. In the course of the growth of the main semiconductor region there occurs a thermal diffusion of aluminum, gallium and indium from the buffer layers into the p-type silicon substrate, with the consequent creation of an alloy layer of the diffused metals. Representing p-type impurities in the p-type silicon substrate, these metals do not create a pn junction in the substrate which causes a forward voltage drop.
摘要翻译：在掺杂有p型杂质的硅衬底上建立发光二极管以具有足够的导电性以提供电流路径。 p型硅衬底在其上外延生长氮化铝和n型氮化铟镓的叠加缓冲层。在缓冲层上外延生长的是LED的主要半导体区域，其包括n型氮化镓的下约束层，用于产生光的有源层和p型氮化镓的上约束层。在主半导体区域的生长过程中，铝，镓和铟从缓冲层发生热扩散到p型硅衬底中，随之产生扩散金属的合金层。在p型硅衬底中表示p型杂质，这些金属在衬底中不产生引起正向压降的pn结。

7. 发明授权

US07173311B2 Light-emitting semiconductor device with a built-in overvoltage protector 有权
标题翻译：具有内置过电压保护器的发光半导体器件
公开(公告)号：US07173311B2
公开(公告)日：2007-02-06
申请号：US11048954
申请日：2005-02-02
申请人： Junji Sato , Koji Otsuka , Tetsuji Moku , Takashi Kato , Arei Niwa , Yasuhiro Kamii
发明人： Junji Sato , Koji Otsuka , Tetsuji Moku , Takashi Kato , Arei Niwa , Yasuhiro Kamii
IPC分类号： H01L23/62
CPC分类号： H01L33/385 , H01L24/05 , H01L27/15 , H01L2224/04042 , H01L2224/05555 , H01L2224/45124 , H01L2224/45144 , H01L2224/48463 , H01L2924/12032 , H01L2924/12035 , H01L2924/12036 , H01L2924/12041 , H01L2924/3011 , H01L2924/3025 , H01L2924/00014 , H01L2924/00
摘要： An overvoltage-proof light-emitting diode has a lamination of light-generating semiconductor layers on a first major surface of a silicon substrate. A front electrode in the form of a bonding pad is mounted centrally atop the light-generating semiconductor layers whereas a back electrode covers a second major surface of the substrate. An overvoltage protector, of which several different forms are disclosed, is disposed between the bonding pad and the second major surface of the substrate. The bonding pad and back electrode serves as electrodes for both LED and overvoltage protector. As seen from above the device, or in a direction normal to the first major surface of the substrate, the overvoltage protector lies substantially wholly beneath the bonding pad.
摘要翻译：耐过电压的发光二极管在硅衬底的第一主表面上层叠有发光半导体层。形成焊盘形式的前电极安装在发光半导体层上方的中央，而后电极覆盖基板的第二主表面。公开了几种不同形式的过电压保护器设置在接合焊盘和衬底的第二主表面之间。接合焊盘和背面电极用作LED和过电压保护器的电极。从设备的上方或者垂直于衬底的第一主表面的方向看，过电压保护器基本上位于接合焊盘的下方。

8. 发明申请

US20050168899A1 Light-emitting semiconductor device with a built-in overvoltage protector 有权
标题翻译：具有内置过电压保护器的发光半导体器件
公开(公告)号：US20050168899A1
公开(公告)日：2005-08-04
申请号：US11048954
申请日：2005-02-02
申请人： Junji Sato , Koji Otsuka , Tetsuji Moku , Takashi Kato , Arei Niwa , Yasuhiro Kamii
发明人： Junji Sato , Koji Otsuka , Tetsuji Moku , Takashi Kato , Arei Niwa , Yasuhiro Kamii
IPC分类号： H01L27/15 , H01L33/38 , H02H9/00
CPC分类号： H01L33/385 , H01L24/05 , H01L27/15 , H01L2224/04042 , H01L2224/05555 , H01L2224/45124 , H01L2224/45144 , H01L2224/48463 , H01L2924/12032 , H01L2924/12035 , H01L2924/12036 , H01L2924/12041 , H01L2924/3011 , H01L2924/3025 , H01L2924/00014 , H01L2924/00
摘要： An overvoltage-proof light-emitting diode has a lamination of light-generating semiconductor layers on a first major surface of a silicon substrate. A front electrode in the form of a bonding pad is mounted centrally atop the light-generating semiconductor layers whereas a back electrode covers a second major surface of the substrate. An overvoltage protector, of which several different forms are disclosed, is disposed between the bonding pad and the second major surface of the substrate. The bonding pad and back electrode serves as electrodes for both LED and overvoltage protector. As seen from above the device, or in a direction normal to the first major surface of the substrate, the overvoltage protector lies substantially wholly beneath the bonding pad.
摘要翻译：耐过电压的发光二极管在硅衬底的第一主表面上层叠有发光半导体层。形成焊盘形式的前电极安装在发光半导体层上方的中央，而后电极覆盖基板的第二主表面。公开了几种不同形式的过电压保护器设置在接合焊盘和衬底的第二主表面之间。接合焊盘和背面电极用作LED和过电压保护器的电极。从设备的上方或者垂直于衬底的第一主表面的方向看，过电压保护器基本上位于接合焊盘的下方。

9. 发明授权

US07186620B2 Method of making substrates for nitride semiconductor devices 有权
标题翻译：制造氮化物半导体器件用基板的方法
公开(公告)号：US07186620B2
公开(公告)日：2007-03-06
申请号：US10995446
申请日：2004-11-23
申请人： Koji Otsuka , Junji Sato , Tomoya Sugahara
发明人： Koji Otsuka , Junji Sato , Tomoya Sugahara
IPC分类号： H01L21/336
CPC分类号： H01L33/007 , C30B25/02 , C30B29/40 , H01L21/0237 , H01L21/02458 , H01L21/02505 , H01L21/0254 , H01L21/0262 , H01L21/02658 , H01L29/2003 , H01L29/66462
摘要： For fabricating an LED substrate with minimal dislocations in its nitride semiconductor layers, GaN is epitaxially grown into a first formative layer overlying a multilayered buffer region on a silicon substrate. A second formative layer is then formed on the first formative layer by epitaxially growing AlN, at such a rate that interstices are created in the first formative layer by the etching action of the reactor gases in the early stages of the fabrication of the second formative layer. Then the second formative layer is etched away from over the intersticed first formative layer, leaving the interstices open. Then a filler layer of GaN is epitaxially grown on the intersticed first formative layer in interfitting engagement therewith. Dislocations are greatly reduced in active semiconductor layers formed subsequently on the filler layer.
摘要翻译：为了制造其氮化物半导体层中具有最小位错的LED衬底，GaN外延生长成覆盖硅衬底上的多层缓冲区的第一形成层。然后通过外延生长AlN在第一形成层上形成第二形成层，其速度是通过在第二形成层的制造的早期阶段通过反应器气体的蚀刻作用在第一形成层中产生空隙。然后将第二形成层从间隙的第一形成层上蚀刻掉，从而使间隙开放。然后，在间隙第一形成层上外延生长GaN的填料层，以与其相互配合接合。填料层随后形成的有源半导体层的位错大大降低。

10. 发明申请

US20050118752A1 Method of making substrates for nitride semiconductor devices 有权
标题翻译：制造氮化物半导体器件用基板的方法
公开(公告)号：US20050118752A1
公开(公告)日：2005-06-02
申请号：US10995446
申请日：2004-11-23
申请人： Koji Otsuka , Junji Sato , Tomoya Sugahara
发明人： Koji Otsuka , Junji Sato , Tomoya Sugahara
IPC分类号： C30B29/38 , C30B25/02 , C30B29/40 , H01L21/20 , H01L21/205 , H01L21/335 , H01L21/338 , H01L29/20 , H01L29/778 , H01L29/812 , H01L33/06 , H01L33/12 , H01L33/32 , H01L33/34 , C30B1/00 , H01L21/336
CPC分类号： H01L33/007 , C30B25/02 , C30B29/40 , H01L21/0237 , H01L21/02458 , H01L21/02505 , H01L21/0254 , H01L21/0262 , H01L21/02658 , H01L29/2003 , H01L29/66462
摘要： For fabricating an LED substrate with minimal dislocations in its nitride semiconductor layers, GaN is epitaxially grown into a first formative layer overlying a multilayered buffer region on a silicon substrate. A second formative layer is then formed on the first formative layer by epitaxially growing AlN, at such a rate that interstices are created in the first formative layer by the etching action of the reactor gases in the early stages of the fabrication of the second formative layer. Then the second formative layer is etched away from over the intersticed first formative layer, leaving the interstices open. Then a filler layer of GaN is epitaxially grown on the intersticed first formative layer in interfitting engagement therewith. Dislocations are greatly reduced in active semiconductor layers formed subsequently on the filler layer.
摘要翻译：为了制造其氮化物半导体层中具有最小位错的LED衬底，GaN外延生长成覆盖硅衬底上的多层缓冲区的第一形成层。然后通过外延生长AlN在第一形成层上形成第二形成层，其速度是通过在第二形成层的制造的早期阶段通过反应器气体的蚀刻作用在第一形成层中产生空隙。然后将第二形成层从间隙的第一形成层上蚀刻掉，从而使间隙开放。然后，在间隙第一形成层上外延生长GaN的填料层，以与其相互配合接合。填料层随后形成的有源半导体层的位错大大降低。

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